14
A+ Server AS -2114GT-DPNR User's Manual
Figure 1-5. Motherboard Layout
PCB EDGE
PCB EDGE
2242
2260
2280
22110
2242
2260
2280
22110
MAC CODE
BAR CODE
1
1
A
C
A37
A1
B37
A37
A1
1
1
1
1
1
1
1
1
1
15
14
5
2
4
1
1
7
1
5
4
8
1
6
15
5
10
11
+
1
+
+
29
30
31
32
B1
A1
B1
A1
B1
A1
B1
A37
A37
B37
A1
A1
B37
A37
B1
1
1
DESIGNED IN USA
H12SSG-AN6
REV:1.00
MAC CODE
BAR CODE
288
144
145
1
222
78
77
221
145
1
222
78
77
221
145
1
222
78
77
221
145
1
222
78
77
221
145
1
222
78
77
221
288
144
145
1
222
78
77
221
288
144
145
1
222
78
77
221
288
144
145
1
222
78
77
221
CY
CK
BK
BY
AY
Y
AK
A
K
+
+
JPCIE2
JPCIE3
JBMC_UART3
JBMC_DEBUG
LED1
JIPMB1
S-UM85
JCOM1
JPCIE_ED1
JPCIE_ED2
JPCIE5
JPCIE6
JMP2
JMP1
MH7
MH6
JU
AR
T2
U93
JMP3
JBT1
LE1
LE2
LEDM1
LED2
JUIDB1
JCPLD1
JDBG4
JPWR4
JPWR3
JPWR2
JPWR1
RT1
JVGA1
BT
1
JTP
M1
JUSBRJ45
JPCIE10
JPCIE11
JPCIE_ED3
JPCIE8
JPCIE7
JPCIE1
JPCIE4
JM2_A1
JM2_B1
JSXB3-2
JSXB2-2
JSXB1-2
JSXB3-1
JSXB1-1
JSXB2-1
J5
J1
J2
J4
J6
J7
J8
MH17
MH16
MH19
SXB1 PCI_E 4.0X16
AIOM1
CPU
R
Q
SXB2 PCI_E 4.0X16
DIMMD1 DIMMC1 DIMMB1
DIMMA1
DIMME1 DIMMF1
DIMMG1 DIMMH1
USB13
(3.0)
USB3
JWD1:W
AT
CH DOG
1-2:RST
2-3:NMI
VGA
USB0/1
(3.0)
IP
MI_LAN
CMOS CLEAR
TP
M/POR
T80
VGA
JIPMB1
BT1
AIOM1
JBT1
USB0/1
COM1
IPMI LAN
JTPM2
UID SW
LED1
LED2
LE2
LE1
LEDM1
JPWR4
JPWR1
JPWR3
JPWR2
JPCIE9
JPCIE8
JMP1
JMP2
JMP3
JPCIE1
JM2_A1 JM2_B1
JPCIE2
JPCIE1
1
JPCIE10
JPCIE3
JPCIE4
JPCI_ED1
JSXB1
JPCI_ED2
JPCIE5
JPCIE6
USB13
JPCI_ED3
JSXB3
JSXB2
DIMMD1
DIMMC1
DIMMB1
DIMMA1
DIMME1
DIMMF1
DIMMG1
DIMMH1
JPCIE7
JWD1
BMC Password Label
