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2-22

BIOS User's Manual

2-4-1 Optimal Default

The Optimal default settings provide optimum performance
settings for all devices and system features.

2-4-2 Fail-Safe Default

The Fail-Safe default settings consist of the safest set of param-
eters. Use them if the system is behaving erratically. They
should always work but do not provide optimal system perfor-
mance characteristics.

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Summary of Contents for 440LX

Page 1: ... SUPER 440LX Chipset AMI BIOS REFERENCE MANUAL Revision 1 1 ...

Page 2: ...IAL INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING FROM THE USE OR INABILITY TO USE THIS PRODUCT OR DOCUMENTATION EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES IN PARTICULAR THE VENDOR SHALL NOT HAVE LIABILITY FOR ANY HARDWARE SOFTWARE OR DATA STORED OR USED WITH THE PRODUCT INCLUDING THE COSTS OF THE REPAIRING REPLACING OR RECOVERING SUCH HARDWARE SOFTWARE OR DATA Copyright 1998 by SUPERMICRO C...

Page 3: ... 3 Chapter 2 Running Setup 2 1 Setup 2 1 1 Standard Setup 2 1 2 1 2 Advanced Setup 2 4 2 1 3 Chipset Setup 2 7 2 1 4 Power Management 2 13 2 1 5 PCI PnP Setup 2 15 2 1 6 Peripheral Setup 2 18 2 2 Security Setup 2 2 1 Supervisor User 2 20 2 2 2 Anti Virus 2 21 2 3 Utility Setup 2 3 1 Language 2 21 2 3 2 Detect IDE 2 21 2 4 Default Setting 2 4 1 Optimal Default 2 22 2 4 2 Fail Safe Default 2 22 BIOS...

Page 4: ...Table of Contents iv Appendix A BIOS Error Beep Codes A 1 Appendix B AMI BIOS POST Diagnostic Error Messages B 1 ...

Page 5: ...PRINTED IN U S A ...

Page 6: ...Standard Archi tecture must have a place to store system information when the computer is turned off The original IBM AT had 64 bytes of non volatile memory storage in CMOS RAM All AT compatible sys tems have at least 64 bytes of CMOS RAM which is usually part of the Real Time Clock Many systems have 128 bytes of CMOS RAM How Data Is Configured AMIBIOS provides a Setup utility in ROM that is acces...

Page 7: ...s EDO Extended Data Out ECC and FPM DRAM supports ECC Error Checking and Correction supports Flash ROM AMIBIOS supports the LS120 drive made by Matsushita Kotobuki Electronics Industries Ltd The LS120 can be used as a boot device is accessible as the next available floppy drive AMIBIOS supports the National Semiconductor LM75 and LM78 data acquisition chips When a failure occurs in a monitored act...

Page 8: ...Floppy Drive A 1 2 MB 5 Display Type VGA EGA Floppy Drive B 1 44 MB 3 Serial Port s 3F8 2F8 AMI BIOS Date 7 15 95 Parallel Port s 378 Processor Clock 200MHz Power Management APM SMI AMIBIOS Setup See the following page for examples of the AMIBIOS Setup screen featuring options and settings Figure 1 1 shows the Standard option highlighted To highlight other options use the arrow keys or use the tab...

Page 9: ...BIOS User s Manual 1 4 Figure 1 1 Standard Option Highlighted Figure 1 2 Settings for Standard Option ...

Page 10: ...and PIO Mode All param eters relate to IDE drives except Type If the hard disk drive to be configured is an IDE drive select the appropriate drive icon choose the Type parameter and select Auto The BIOS will automatically detect the IDE drive parameters and display them Click on the OK button to accept these param eters Click on LBA Large Mode and choose On to enable support for IDE drives with ca...

Page 11: ...23 17 60 MB 20 733 5 300 732 17 30 MB 21 733 7 300 732 17 43 MB 22 733 5 300 733 17 30 MB 23 306 4 0 336 17 10 MB 24 925 7 0 925 17 54 MB 25 925 9 65535 925 17 69 MB 26 754 7 754 754 17 44 MB 27 754 11 65535 754 17 69 MB 28 699 7 256 699 17 41 MB 29 823 10 65535 823 17 68 MB 30 918 7 918 918 17 53 MB 31 1024 11 65535 1024 17 94 MB 32 1024 15 65535 1024 17 128 MB 33 1024 5 1024 1024 17 43 MB 34 612...

Page 12: ...te precompensation begins Landing Zone This number is the cylinder location where the heads will normally park when the system is shut down Sectors The number of sectors per track MFM drives have 17 sectors per track RLL drives have 26 sectors per track ESDI drives have 34 sectors per track SCSI and IDE drive may have even more sectors per track Capacity The formatted capacity of the drive is Numb...

Page 13: ...D Floppy ARMD FDD ARMD HDD or ATAPI CD ROM The options for the 4th Boot Device are Disabled 1st IDE HDD 2nd IDE HDD 3rd IDE HDD 4th IDE HDD Floppy ARMD FDD ARMD HDD The Disabled option in the 4th boot device means that setup will not be considered during the boot process 1st IDE HDD 2nd IDE HDD 3rd IDE HDD and 4th IDE HDD are the four hard disks than can be installed by the BIOS 1st IDE HDD is the...

Page 14: ...ermines the display screen with which the POST is going to start the display The settings for this option are BIOS or Silent If selected as BIOS the POST will start with the normal sign on message screen If Silent is selected the POST will start with the silent screen Display Mode at Add on ROM Init This option determines the display mode during add on ROM except Video add on ROM initialization Th...

Page 15: ...e Primary Display This option specifies the type of display adapter card installed in the system The settings are Absent VGA EGA CGA40x25 CGA80x25 or Mono Password Check This option enables the password check option every time the system boots or the end user runs WinBIOS Setup If Always is chosen a user password prompt appears every time the com puter is turned on If Setup is chosen the password ...

Page 16: ...are not only copied from ROM to RAM the contents of the C0000h C7FFFh RAM can be written to or read from cache memory C800 16K Shadow CC00 16K Shadow D000 16K Shadow D400 16K Shadow D800 16K Shadow DC00 16K Shadow These options specify how the contents of the adaptor ROM named in the option title are handled The ROM area that is not used by ISA adapter cards will be allocated to PCI adapter cards ...

Page 17: ...x333 or x222 EDO Write Burst Timing Burst mode EDO have internal column counters Because of this they do not need to accept row addresses and starting column addresses from the EDO memory controller This eliminates the setup and hold time for the second and subsequent column addresses It also improves the EDO Write access time The settings for this option are x333 or x222 EDO RAS Precharge Memory ...

Page 18: ...rite Combining The settings are Disabled or Enabled PCI Frame Buffer USWC The settings for this option are Disabled or Enabled When Enabled the PCI frame buffer address and length are divided into 2 The value is then programmed into the processor Variable MTRR 3 with the value for USWC 01h DRAM Integrity Mode ECC The settings for this option are Non ECC EC only or ECC Set this option to Enabled to...

Page 19: ...be updated by the PAC specific BIOS configuration sequence before PCI standard bus enumeration sequence takes place If the register is not updated a default value selects aperture of maximum size i e 256 MB The settings are 4 MB 8 MB 16 MB 32 MB 64 MB 128 MB or 256 MB System Type The settings are Auto DP or UP USWC Write I O Post Use this feature for the WC Write Post During I O Bridge Access Enab...

Page 20: ...to Enabled the PAC s SERR signal driver is enabled and SERR is asserted for all relevant bits set in the ERRSTS and PCISTS as controlled by the corresponding bits of the ERRCMD register When Disabled SERR is never driven by the PAC AGP Common SERR The settings are Disabled or Enabled Set to Enabled to permit a common SERR signal for AGP and the standard PCI bus AGP System Error Forwarding The sett...

Page 21: ...ettings are Disabled or Enabled Master Lat Timer Master Latency Timer is an 8 bit register that controls the amount of time the PAC as a PCI bus master can burst data on the PCI bus The count value is an 8 bit quantity However MLT 2 0 are 0 when determining the count value The PAC s MLT is used to guarantee to the PCI agents other than PAC a minimum amount of the system resources Note Settings are...

Page 22: ...gs for power supply type are AT or ATX Instant on Support Instant on is one of ACPI s standard features The system comes back on instantly from ACPI s SoftOff state The settings are Disabled or Enabled Green PC Monitor Power State This option specifies the power state that the green PC compliant video monitor enters when AMIBIOS places it in a power savings state after the specified period of disp...

Page 23: ...inutes This option specifies the length of a period of system inactivity while in standby state When this length of time expires the computer enters suspend power state The settings are Disabled and 4 Min through 508 Min in 4 minute intervals Slow Clock Ratio The value of the slow clock ratio indicates the percentage of time the STPCLK signal is asserted while in the thermal throttle mode The sett...

Page 24: ...ou must set this option correctly Otherwise PnP aware adapter cards installed in the computer will not be config ured properly PCI Latency Timer PCI Clocks This option specifies the latency timings in PCI clocks for all PCI devices The settings are 32 64 96 128 160 192 224 or 248 PCI VGA Palette Snoop The settings for this option are Disabled or Enabled When set to Enabled multiple VGA devices ope...

Page 25: ... is installed Slot 1 Slot 2 Slot 3 Slot 4 Slot 5 or Slot 6 This option forces IRQ14 and IRQ15 to a PCI slot on the PCI local bus This is necessary to support non compliant ISA IDE control ler adapter cards If an offboard PCI IDE controller adapter card is installed in the computer you must also set the Offboard PCI IDE Primary IRQ and Offboard PCI IDE Secondary IRQ options Offboard PCI IDE Primary...

Page 26: ...e IRQs must be removed from the pool the end user can use these options to reserve the IRQ by assigning an ISA EISA setting to it Onboard I O is configured by AMIBIOS All IRQs used by onboard I O are configured as PCI PnP IRQ14 and 15 will not be available if the onboard PCI IDE is enabled If all IRQs are set to ISA EISA and IRQ14 and 15 are allocated to the onboard PCI IDE IRQ 9 will still be ava...

Page 27: ... AMIBIOS automatically determines the correct base I O port address Disabled 3F8h 2F8h 3E8h or 2E8h OnBoard Serial Port 2 This option specifies the base I O port address of serial port 2 The settings are Auto AMIBIOS automatically determines the correct base I O port address Disabled 3F8h 2F8h 3E8h or 2E8h Serial Port 2 Mode The settings are Normal Sharp IR IrDA or TV Remote IR Duplex Mode The set...

Page 28: ...re Auto 5 or 7 Parallel Port DMA Channel This option is only available if the setting of the parallel port mode option is ECP The settings are 0 1 2 3 5 6 or 7 Note The Optimal and Fail Safe default settings are N A OnBoard IDE This option specifies the onboard IDE controller channels to be used The settings are Disabled Primary Secondary or Both OnBoard NAT307 Mode Set The settings for this optio...

Page 29: ... 1 LM78 In1 CPU 2 LM78 In2 3 3V LM78 In3 5V LM78 In4 12V LM78 In5 12V LM78 In6 5V CPU1 Fan CPU2 Fan Chassis Fan The above features are for the onboard National Semiconductor s LM 78 System Hardware Monitor used for PC health monitoring The motherboards with LM 78 have seven onboard voltage monitors for the CPU core CPU I O 3 3V 5V 5V 12V and 12V and three fan status monitors 2 2 Security Setup 2 2...

Page 30: ...password The password does not appear on the screen when typed Retype the new password as prompted and press Enter Make sure you write it down If you forget it you must drain CMOS RAM and reconfigure 2 2 2 Anti Virus When this icon is selected AMIBIOS issues a warning when any program or virus issues a disk format command or attempts to write to the boot sector of the hard disk drive The settings ...

Page 31: ...um performance settings for all devices and system features 2 4 2 Fail Safe Default The Fail Safe default settings consist of the safest set of param eters Use them if the system is behaving erratically They should always work but do not provide optimal system perfor mance characteristics ...

Page 32: ... error messages normally appear on the screen Fatal errors are those which will not allow the system to continue the boot up procedure If a fatal error occurs you should consult with your system manufacturer for possible repairs These fatal errors are usually communicated through a series of audible beeps The numbers on the fatal error list on the follow ing page correspond to the number of beeps ...

Page 33: ...A20 switch which allows the CPU to operate in virtual mode This error means that the BIOS cannot switch the CPU into protected mode 7 Processor Exception The CPU on the motherboard generated Interrupt Error an exception interrupt 8 Display Memory Read Write The system video adapter is either Error missing or its memory is faulty Please Note This is not a fatal error 9 ROM Checksum Error The ROM ch...

Page 34: ...ler If it still beeps try a different keyboard or replace the keyboard fuse if the keyboard has one 8 times there is a memory error on the video adapter Replace the video adapter or the RAM on the video adapter 9 times the BIOS ROM chip is bad The system probably needs a new BIOS ROM chip 11 times reseat the cache memory on the motherboard If it still beeps replace the cache memory 4 5 7 the mothe...

Page 35: ...BIOS User s Manual A 4 ...

Page 36: ...e CPU data area 08 The CMOS checksum calculation is done next OB Next performing any required initialization before keyboard BAT command is issued 0C The keyboard controller I B is free Next issuing the BAT command to the keyboard controller 0E The keyboard controller BAT command result has been verified Next performing any necessary initialization after the keyboard controller BAT command test 0F...

Page 37: ...memory refresh test line is toggling Checking the 15 second on off time next 23 Reading the 8042 input port and disabling the MEGAKEY Green PC feature next Making the BIOS code segment writable and perfoming any necessary configuration before initializing the interrupt vectors 24 The configuration required before interrupt vector initialization has completed Interrupt vector initialization is done...

Page 38: ...rocessing If the EGA VGA controller is not found performing the display memory read write test next 2F The EGA VGA controller was not found The display memory read write test is about to begin 30 The display memory read write test passed Look for retrace checking next 31 The display memory read write test or retrace checking failed Performing the alternate display memory read write test next 32 Th...

Page 39: ...next 46 The memory wraparound test has completed The memory size calculation has been completed Writing patterns to test memory next 47 The memory pattern has been written to extended memory Writing patterns to the base 640 KB memory next 48 Patterns written in base memory Determining the amount of memory below 1 MB next 49 The amount of memory below 1 MB has been found and verified Determining th...

Page 40: ...lay was adjusted for relocation and shadowing Testing the memory above 1 MB next 52 The memory above 1 MB has been tested and initialized Saving the memory size information next 53 The memory size information and the CPU registers are saved Entering real mode next 54 Shutdown was successful The CPU is in real mode Disabling the Gate A20 line parity and the NMI next 57 The A20 address line parity a...

Page 41: ...as found Issuing the keyboard controller interface test command next 82 The keyboard controller interface test completed W riting the command byte and initializing the circular buffer next 83 The command byte was written and global data initialization has been completed Checking for a locked key next 84 Locked key checking is over Checking for a memory size mismatch with CMOS RAM data next 85 The ...

Page 42: ...ammed Resetting the hard disk controller next 8F The hard disk controller has been reset Configuring the floppy drive controller next 91 The floppy drive controller has been configured Configuring the hard disk drive controller next 95 Initializing the bus option ROMs from C800 next 96 Initializing before passing control to the adaptor ROM at C800 97 Initialization before the C800 adaptor ROM gain...

Page 43: ...yboard ID and Num Lock key next Issuing the keyboard ID command next A2 Displaying any soft errors next A3 The soft error display has completed Setting the keyboard typematic rate next A4 The keyboard typematic rate is set Programming the memory wait states next A5 Memory wait state programming is over Clearing the screen and enabling parity and the NMI next A7 NMI and parity enabled Performing an...

Page 44: ...has completed Displaying the system configuration next AB Building the multiprocessor table if necessary POST next B0 The system configuration is displayed AC Uncompressing the DMI data and initializing DMI B1 Copying any code to specific areas 00 Code copying to specific areas is done Passing control to INT 19h boot loader next ...

Page 45: ...BIOS User s Manual B 10 ...

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