Super X8DT3, User Manual

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Chapter 1: Introduction
1-9
1-3 Chipset Overview
Built upon the capability of the Intel 5520 platform, the X8DT3/X8DTi/X8DT3-F/
X8DTi-F/X8DT3-LN4F/X8DTi-LN4F motherboard provides the performance and
feature set required for dual-processor-based high-end systems with confi gura-
tion optimized for workstations, High Performance Computing (HPC) systems,
and intensive applications. The 5520 platform consists of the 5500 Series (LGA
1366) processor, the 5520 (North Bridge), and the ICH10R (South Bridge). With
the QuickPath Interconnect (QPI) controller built in, the 5520 platform is the fi rst
dual-processing platform that offers the next generation point-to-point system
interconnect interface to replace the current Front Side Bus Technology, substan-
tially enhancing system performance with increased bandwidth and scalability.
The 5520 North Bridge connects to each processor through an independent Quick-
Path Interconnect link. Each link consists of 20 pairs of unidirectional differential
lanes for data transferring in addition to a differential forwarded clock. A full-width
QuickPath interconnect link pair provides 84 signals. Each processor supports two
QuickPath links, one going to the other processor and the other to the 5520.
The 5520 platform supports up to 36 PCI Express Gen2 lanes, peer-to-peer read
and write transactions. The ICH10R provides up to 6 PCI-Express ports, six SATA
ports and 10 USB connections.
In addition, the 5520 platform also offers a wide range of RAS (Reliability, Avail-
ability and Serviceability) features. These features include memory interface ECC,
x4/x8 Single Device Data Correction (SDDC), Cyclic Redundancy Check (CRC),
parity protection, out-of-band register access via SMBus, memory mirroring,
memory sparing, and Hot-plug support on the PCI-Express Interface.
Main Features of the 5500 Series Processor and the 5520
Chipset
Four processor cores in each processor with 8MB shared cache among cores
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Two full-width Intel QuickPath interconnect links, up to 6.4 GT/s of data transfer
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rate in each direction
Virtualization Technology, Integrated Management Engine supported
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Point-to-point cache coherent interconnect, Fast/narrow unidirectional links, and
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Concurrent bi-directional traffi c
Error detection via CRC and Error correction via Link level retry
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