Super X10DRi, User Manual

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X10DRi/X10DRi-T User’s Manual
No PCIe Port Active ECO
Use this feature to select a workaround setting to implement the engineering-
change order (ECO) on the system when PCI ports are not active. The options
are
PCU Squelch exit ignore option and Reset the SQ FLOP by CSR option.

IOAT Configuration
Enable I/OAT
Select Enable to enable Intel I/OAT (I/O Acceleration Technology), which signifi -
cantly reduces CPU overhead by leveraging CPU architectural improvements
and freeing the system resource for other tasks. The options are Enable and
Disable .
No Snoop
Select Enable to support no-snoop mode for each CB device. The options are
Disable and Enable.
Relaxed Ordering
Select Enable to enable Relaxed Ordering support which will allow certain trans-
actions to violate the strict-ordering rules of PCI and to be completed prior to
other transactions that have already been enqueued. The options are
Disable
and Enable.

Intel VT for Directed I/O (VT-d)
Intel VT for Direct I/O (VT-d)
Intel
®
VT for Directed I/O (VT-d)
Select Enable to use Intel Virtualization Technology support for Direct I/O VT-d
support
by reporting the I/O device assignments to the VMM (Virtual Machine
Monitor) through the DMAR ACPI tables. This feature offers fully-protected I/O
resource sharing across Intel platforms, providing greater reliability, security and
availability in networking and data-sharing. The options are
Enable and Disable.
Interrupt Remapping
Select Enable for Interrupt Remapping support to enhance system performance.
The options are
Enable and Disable.
Coherency Support (Non-Isoch)
Select Enable for the Non-Iscoh VT-d engine to pass through DMA (Direct
Memory Access) to enhance system performance. The options are Enable and
Disable .
Use this item to set the limit on power performance states for the run-time processor,
with P0 being the state with the highest power and frequency, and P1, a step lower in
performance than P0, with its voltage and frequency scaled back a notch. The options
are Between P1/P0 and Below P1.