Sundance Spas SMT398, User Manual

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Version 1.1.1 Page 14 of 38 SMT398 User Manual
CONFIG is driven from another TIM site on the carrier board, for instance, from a
DSP module running an application. (See
General Firmware Description for
information on the DSP TIM CONFIG signal.)
After a Global Reset pulse, a DSP module drives CONFIG low and keeps it low by
default.
After Reset and loading of the DSP application, CONFIG can be driven the following
way:
#include “SMT3xx.h”
#define CONFIG_BIT 1<<6
int main()
{
*CONFIG |= CONFIG_BIT; //tristates CONFIG (Pull-ups on the carrier board pull CONFIG high)
*CONFIG &= (UINT32)~CONFIG_BIT;//CONFIG is driven low
//delay while the FPGA is configured
*CONFIG |= CONFIG_BIT;
}
This feature can be interesting in systems where:
•
The FPGA needs to implement multiple functions spread in different
bitstreams that are needed at different stages of the application.
•
The system needs to keep running and can’t be interrupted by a global Reset
pulse when the FPGA needs to be configured with a new bitstream.
Notes:
•
TIM CONFIG is only available on SMT398 v3. The SMT398 version is written
on TOP of the board (See
Figure 10:SMT398 Components placement-Top
view ).
•
TIM CONFIG needs CPLD code version 2.1 or above (Written on a sticker on
the CPLD. (See
Figure 10:SMT398 Components placement-Top view ).
•
The ComPort3 is reserved for the CPLD and cannot be made available to the
FPGA.
•
CONFIG needs switch SW1 position 8 to be ON. (See Figure 11: SMT398
Components placement-Bottom view )
Virtex II Bitstream Format
The Virtex II SelectMap interface is an 8-bit interface on the device with data pins
labeled D[7:0]. The configuration bitstreams can be written eight bits per clock cycle.
The Virtex II configuration bitstreams generated by BitGen (.bit files) contain a mix of
commands and data on 32 bit word boundaries, shown in
Xilinx application note 138
page 20. This format assumes D0 is considered the MSBit as shown Figure 4: V II
Configuration Bitstream Word Format .