Version 1.1.1
Page 13 of 38
SMT398 User Manual
The CPLD does not implement any operation on the bitstream and passes it straight
through to the FPGA once the STARTKEY has been decoded and until the ENDKEY
is decoded.
Once the FPGA DONE pin has gone high, LED L5 (See
, bottom right hand corner of the picture) becomes
on, indicating that the FPGA configured.
The CPLD disables the SelectMap interface and waits for the ENDKEY command on
ComPort3.
Once the ENDKEY command is received, the CPLD releases ComPort 3.
Reset Control
TIM Global Reset
The CPLD is connected to a TIM global Reset signal provided to the SMT398 via its
TIM connector J4 pin 30. (See
Figure 10:SMT398 Components placement-Top view
The TIM global Reset signal is also available for the FPGA but the CPLD provides
another signal called
FPGAResetn
that offers a better Reset control over the FPGA.
At power up or on reception of a low TIM global Reset pulse, the CPLD drives the
FPGAResetn signal low and keeps it low.
When the ENDKEY has been received, the CPLD drives FPGAResetn high.
I recommend that you use
FPGAResetn
for the Global Reset signal of your FPGA
designs.
In this manner, you can control your FPGA design Reset activity and you will also
avoid possible conflicts on ComPort 3 if your FPGA design implements it.
TIM CONFIG
On The CPLD is connected a TIM CONFIG signal provided to the SMT398 via its
TIM connector J4 pin 74. (See
Figure 10:SMT398 Components placement-Top view
and
Figure 8:SMT398 ComPorts connections
CONFIG falling has the same effect on the SMT398 CPLD as a TIM global Reset
pulse.
On detection of a falling edge on the CONFIG line, the CPLD drives the FPGAResetn
signal low and keeps it low.
CONFIG provides a means of reprogramming the FPGA without having to drive the
TIM Global Reset signal.
Therefore any other modules sensitive to the TIM global Reset signal will not be
affected and can keep running their application.
Summary of Contents for SMT398
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