Preliminary
Page 16 of 16
SMT327 User Guide
Document Name:
User Guide
Issue : 01
Rev 02
Product Name:
SMT327
Revision Date:
8 August, 2000
Author:
Bill Blyth
Original Date:
30 April 1998
9.3 Status Register (Offset 14h)
The STATUS register can only be read.
OBE IE
Set if comport output buffer empty interrupts enabled.
IBF IE
Set if comport input buffer full interrupts enabled
TBC IE
Set if JTAG interrupts enabled
C40 IE
Set if interrupt from TIM1 C40 enabled
OBE INT
Set if comport output buffer becomes empty.
Cleared by writing a 1 to the corresponding bit in the interrupt control
register.
IBF INT
Set if comport input buffer receives a word.
Cleared by writing a 1to the corresponding bit in the interrupt control
register
TBC INT
Set when the TBC asserts its interrupt.
Cleared by removing the source of the interrupt in the TBC.
C40 INT
Set when the TIM1 C40 sets its host interrupt bit.
Cleared by writing a 1 to the corresponding bit in the interrupt control
register.
INTA
This is a logical OR of bits 7 to 4 in this register gated with each
ones enable bit.
OBF
Set when a word is loaded into the comport output register. Cleared
when the word is transmitted to the C40.
IBF
Set when a word is received into the comport input register from the
TIM1 C40.
MASTER
When set, the comport interface token is owned by the SMT320
bridge.
TBC RDY
Reflects the current state of the TBC RDY pin. This bit is active high
and therefore and inversion of the TBC pin.
CONFIG_L
Reflects the current state of the CONFIG signal from the TIM1 C40.
Active low.
Bit
31:22
21
20
19
18
17
16
Name
X
CONFIG_L
TBC RDY
0
MASTER
IBF
OBF
Bit
15
14
13
12
11
10
9
8
Name
X
X
X
X
X
X
X
INTA
Bit
7
6
5
4
3
2
1
0
Name
C40 INT
TBC
INT
IBF
INT
OBE
INT
C40 IE TBC IE
IBF IE
OBE
IE
