manualshive.com logo in svg

Sundance Spas SMT327, User Manual

Share
Download
Sundance Spas SMT327 User Manual Download Page 12

Preliminary 

Page 12 of 12

 

SMT327 User Guide 

 

Document Name: 

User Guide 

Issue : 01 

Rev 02 

Product Name: 

SMT327 

Revision Date: 

8 August, 2000 

Author: 

Bill Blyth 

Original Date: 

30 April 1998 

 

Pin 

Signal 

Direction 

Description 

1 

TDO 

OUT 

JTAG data out 

2 

GND 

 

 

3 

TDI 

IN 

JTAG data in 

4 

GND 

 

 

5 

TMS 

OUT 

JTAG Test mode select 

6 

GND 

 

 

7 

TCK 

OUT 

JTAG clock 10MHz 

8 

GND 

 

 

9 

TCK_RET 

IN 

JTAG clock return 

10 

GND 

 

 

11 

-TRST 

OUT 

JTAG Reset 

12 

GND 

 

 

13 

-RESET 

OUT 

Board Reset out 

14 

PD 

IN 

Presence detect when pulled 

high 

15 

-DETECT 

OUT 

Detect external JTAG 

controller when grounded 

16 

CONFIG 

OPEN COLL 

Global open collector C4x 

CONFIG 

17 

EMU0 

IN 

EMU0 input 

18 

EMU1 

IN 

EMU1 input 

19 

SPARE1 

 

 

20 

SPARE2 

 

 

Table 3 JTAG Master Port (Output) 

Summary of Contents for SMT327

Page 1: ...Preliminary Document Name User Guide Issue 01 Rev 02 Product Name SMT327 Revision Date 8 August 2000 Author Bill Blyth Original Date 30 April 1998 SMT327 Compact PCI 4 SLOT MOTHERBOARD User Guide ...

Page 2: ...AL COMMUNICATION PORTS 13 9 REGISTERS 14 9 1 COMPORT REGISTERS OFFSET 10H 14 9 2 CONTROL REGISTER OFFSET 14H 15 9 3 STATUS REGISTER OFFSET 14H 16 9 4 INTERRUPT CONTROL REGISTER OFFSET 18H 17 9 5 TEST BUS CONTROLLER TBC OFFSETS 80H AFH 17 10 BRIDGE C40 OPERATION 19 10 1 8 1 FIFO 19 10 2 8 2 PCI ADDRESS 20 10 3 8 3 C40 CONTROL REGISTER 20 11 PHYSICAL CHARACTERISTICS 21 11 1 POWER CONSUMPTION 21 11 2...

Page 3: ...iminary Page 3 of 3 SMT327 User Guide Document Name User Guide Issue 01 Rev 02 Product Name SMT327 Revision Date 8 August 2000 Author Bill Blyth Original Date 30 April 1998 Figure 4 Master Mode Interface 19 ...

Page 4: ...pactPCI specification Four TIM slots Two internal communication port pipelines TIM to TIM communication ports are non buffered for highest speed All 6 front panel communication ports are fully buffered On board JTAG debugging circuit accessed from PCI supports Code Composer External JTAG access with master and slave ports Master mode for TIM slot 0 allows global bus access to PCI memory space C40 ...

Page 5: ...am see 3L s C40 Technical Note 62 TISLINK SMT320 INDEX 0 DEVICE 0327 A new 3L TIS loader program for Windows 95 TIS_WD32 EXE is supplied with the SMT327 This must be copied into your 3L installation directory usually TIC2V0 copy a tis_wd32 exe c tic2v2 tis exe You will be requested if you wish to overwrite the original in this directory This is required as the present version of TIS is not a prote...

Page 6: ...n ports 2 and 5 of each TIM in common with the SMT320 In addition all other communication ports are available using FMS 14 connectors for inter TIM connections Two further pipes using ports 0 3 and 1 4 of each TIM can be broken to allow other topologies to be constructed These pipes use logic to detect when a cable is inserted to avoid contention between the pipe and the desired connection PCI Bus...

Page 7: ...ach pair of TIM s Each patch area has 3 front panel FMS connectors that allow a communication port to be buffered to a front panel connector Buffered communication ports can be used between SMT327 boards or other compatible systems at distances up to 0 8m The diagram below details the layout of the TIM slots and potential routing of the flat flexible cables Front Panel Area T1C0 O FP0 O J1 J2 TIM ...

Page 8: ...g outwards The connection between internal communication ports of the form TxCy must use the rule that RTO and RTI ports are the only valid connection Like ports must never be connected using FMS cables as these ports are unprotected except for some series termination with damage a likely outcome Connections in the patch area to the front panel FMS connectors FPn I O must match RTO to RTO and RTI ...

Page 9: ...Out RTO ports by default and represent a similarly numbered port within the SMT327 The right side ports 3 5 are Reset To In RTI IMPORTANT In all system configurations RTO ports should only be connected to RTI ports This applies to internal flat cable connections as well as buffered port connections Because of the high current drivers used in the buffered ports protection is built in and will cause...

Page 10: ...ses a 3M MDR style 26 way connector These buffered communications ports are compatible with the Sundance SMT328 VME TIM carrier Pin Twisted Pair Signal 1 1 STRB 2 1 GND 3 2 RDY 4 2 GND 5 3 REQ 6 3 GND 7 4 ACK 8 4 GND 9 5 DIR_OUT 10 5 GND 11 6 DIR_IN 12 6 GND 13 7 D0 14 7 D1 15 8 D2 16 8 D3 17 9 D4 18 9 D5 19 10 D6 20 10 D7 21 11 VCC 22 11 GND 23 12 RESET_OUT 24 12 GND 25 13 SPARE 26 13 GND SHELL S...

Page 11: ... become a JTAG master with no connections or with a slave SMT327 connected to the JTAG OUT port An SMT327 that detects a cable connection on its JTAG IN port automatically becomes a slave and routes the TAP port accordingly Pin Signal Direction Description 1 TDI IN JTAG data in 2 GND 3 TDO OUT JTAG data out 4 GND 5 TMS IN JTAG Test mode select 6 GND 7 TCK IN JTAG clock up to 10MHz 8 GND 9 TCK_RET ...

Page 12: ... TDI IN JTAG data in 4 GND 5 TMS OUT JTAG Test mode select 6 GND 7 TCK OUT JTAG clock 10MHz 8 GND 9 TCK_RET IN JTAG clock return 10 GND 11 TRST OUT JTAG Reset 12 GND 13 RESET OUT Board Reset out 14 PD IN Presence detect when pulled high 15 DETECT OUT Detect external JTAG controller when grounded 16 CONFIG OPEN COLL Global open collector C4x CONFIG 17 EMU0 IN EMU0 input 18 EMU1 IN EMU1 input 19 SPA...

Page 13: ...rd communication links These 14 pin connectors are configured as shown below FMS Pin Signal FMS Pin Signal 1 DIS 1 GND 2 D0 2 D0 3 D1 3 D1 4 D2 4 D2 5 D3 5 D3 6 D4 6 D4 7 D5 7 D5 8 D6 8 D6 9 D7 9 D7 10 REQ 10 REQ 11 ACK 11 ACK 12 STRB 12 STRB 13 RDY 13 RDY 14 GND 14 DIS RTI Ports RTO Ports Table 4 FMS Connector Note that these connectors have sense pins to detect when a cable is inserted This avoi...

Page 14: ...ress space is decoded as shown in the table below Offset Register Write Register Read Width 0 4 8 0C 10 COMPORT_OUT COMPORT_IN 32 14 CONTROL STATUS 32 18 INT_CONTROL 32 1C 20 to 3F Not used Not used 40 to 7E Mailbox Write Mailbox Read 32 80 to AF TBC Write TBC Read 16 9 1 Comport Registers Offset 10h The host is connected to the first TIM site using comport 3 This port is bi directional and will a...

Page 15: ...IM site Boot Control Note On PCI system reset RESET is asserted to all TIM sites Bit 7 5 4 3 2 1 0 Name Not used notNMI IIOF2 IIOF1 IIOF0 RESET RESET Write a 1 to this bit to assert the reset signal to all TIM modules on the SMT320 IIOF0 IIOF1 IIOF2 These bits connect to the corresponding pins on the first TIM site These bits are open drain and can only pull down If not required before or after bo...

Page 16: ...Cleared by removing the source of the interrupt in the TBC C40 INT Set when the TIM1 C40 sets its host interrupt bit Cleared by writing a 1 to the corresponding bit in the interrupt control register INTA This is a logical OR of bits 7 to 4 in this register gated with each ones enable bit OBF Set when a word is loaded into the comport output register Cleared when the word is transmitted to the C40 ...

Page 17: ...enerated when the host comport register has transmitted its contents TBC IE Test Bus Controller Interrupt Enable Interrupts from the Texas JTAG controller are enabled when set C40 IE C40 Interrupt Enable Allows a programmed interrupt to be generated by the C40 when set CLEAR OBE INT Write a one to this bit to clear the interrupt resulting from a comport output event CLEAR IBF INT Write a one to th...

Page 18: ...ommand Major Command 98 Counter 1 Update 0 Counter 1 Update 0 9A Counter 1 Update 1 Counter 1 Update 1 9C Counter 2 Update 0 Counter 2 Update 0 9E Counter 2 Update 1 Counter 2 Update 1 A0 Status 0 A2 Status 1 A4 Status 2 A6 Status 3 A8 Capture 0 AA Capture 1 AC Read Buffer AE Write Buffer The organisation of the TBC registers is of a stack of 16 bit registers aligned to 16 bit boundaries They are ...

Page 19: ...6 deep x 32 wide FIFO buffers on both read and write paths between the C40 and PCI bus The FIFO is only effective when burst mode is enabled in the control register With burst mode disabled the bridge will request the PCI bus for each word transferred With burst mode enabled data written to the empty FIFO will be absorbed until 16 words make the FIFO full This state will trigger a PCI burst write ...

Page 20: ...to the address register loses the bottom two bits in order to match the PCI bus mode used by the bridge The address counter increments on every valid PCI to track the source or destination pointer in the event of a target disconnect The bridge may disconnect during burst transfers but this will be transparent to the C40 10 3 8 3 C40 Control Register The Control register provides the C40 interface ...

Page 21: ... board requires both 5v and 3V3 from the CompactPCI connector These must be provided to avoid damage to the PCI bridge Without TIM s the consumption from 5V is less than 3A and from 3V3 is less than 0 5A 11 2 Board Dimensions The board conforms to the COMPACTPCI standard for a 6U board This is 160 0 0 0 3 mm by 233 35 0 0 3 mm The board occupies 2 COMPACTPCI slots by virtue of the front panel conn...

Reviews:

No comments

Brands by name

Popular brands

Load more brands