Preliminary
Page 15 of 15
SMT327 User Guide
Document Name:
User Guide
Issue : 01
Rev 02
Product Name:
SMT327
Revision Date:
8 August, 2000
Author:
Bill Blyth
Original Date:
30 April 1998
9.2 Control Register (Offset 14h)
The CONTROL register can only be written. It contains flags which control the boot modes of the first TIM
site.
Boot Control
Note. On PCI system reset, RESET is asserted to all TIM sites.
Bit
7-5
4
3
2
1
0
Name
Not used
notNMI
IIOF2
IIOF1
IIOF0
RESET
RESET
Write a 1 to this bit to assert the reset signal to all TIM modules on the
SMT320.
IIOF0
IIOF1,
IIOF2
These bits connect to the corresponding pins on the first TIM site. These
bits are open-drain and can only pull down. If not required before or after
booting they should be written with 1’s.
NotNMI
A 0 written to this bit will assert the active low NMI to the TIM1 C40.
