Sun Microsystems SPARCengine Ultra AXi, Technical Manual

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Chapter 2 Specification Summary 2-5
2.1.5 Ethernet 10/100 BASE-T Interface
Interface Connector RJ-45, 8-pin connector
Bootable via Network
Data Bit rate 10BASE-T @ 10Mbits/sec
100 BASE-T @ 100Mbits/sec
IEEE 802.3u Auto Negotiation
External Cables Category 3, 4 or 5 unshielded twisted pair cable,
1000 Meter max for 10BASE-T operation
Category 5 unshielded twisted pair cable,
100 Meter max for 100BASE-T operation
2.1.6 PCI Connectors
Compatibility Compliant with PCI Rev 2.1 specifications
Full 32bit support
Interface connector 62-pin PCB edge connector,
See A.3.5 on page A-15
Will accept long card or short card
Can support up to 25W per slot depending upon
the power supply selected
PCI-Bus segments 3 slots on PCI-A (bus segment)
3 slots on PCI-B (bus segment)
PCI-A and PCI-B segments are functionally identical
Signalling Interface level ‘5V signalling’ only
Supports 33MHz operation only
Address space 2GB address space within the same bus segment
2GB address space beyond its bus segment
IO, memory, configuration space mapped into
UltraSPARC
PCI address space is NON-CACHEABLE
Transactions All types and modes of PCI transactions are supported
Peer to peer transfers possible within the same bus
segment
Direct Data Transfers between bus segments are not
supported
Data transfer rates In PIO mode 124MB/s max
In DMA mode, read 78MB/s max
In DMA mode, write 124MB/s max