Ethernet (ETH): media access control (MAC) with DMA controller
RM0090
1150/1731
DocID018909 Rev 11
Figure 372. Networked time synchronization
1.
The master broadcasts PTP Sync messages to all its nodes. The Sync message
contains the master’s reference time information. The time at which this message
leaves the master’s system is t
1
. For Ethernet ports, this time has to be captured at the
MII.
2. A slave receives the Sync message and also captures the exact time, t
2
, using its
timing reference.
3. The master then sends the slave a Follow_up message, which contains the t
1
information for later use.
4. The slave sends the master a Delay_Req message, noting the exact time, t
3
, at which
this frame leaves the MII.
5. The master receives this message and captures the exact time, t
4
, at which it enters its
system.
6. The master sends the t
4
information to the slave in the Delay_Resp message.
7. The slave uses the four values of t
1
, t
2
, t
3
, and t
4
to synchronize its local timing
reference to the master’s timing reference.
Most of the protocol implementation occurs in the software, above the UDP layer. As
described above, however, hardware support is required to capture the exact time when
specific PTP packets enter or leave the Ethernet port at the MII. This timing information has
to be captured and returned to the software for a proper, high-accuracy implementation of
PTP.
Reference timing source
To get a snapshot of the time, the core requires a reference time in 64-bit format (split into
two 32-bit channels, with the upper 32 bits providing time in seconds, and the lower 32 bits
indicating time in nanoseconds) as defined in the IEEE 1588 specification.
The PTP reference clock input is used to internally generate the reference time (also called
the System Time) and to capture time stamps. The frequency of this reference clock must
Master clock time
Slave clock time
Data at
slave clock
Sync message
Follow_up message
containing value of t1
Delay_Re
q
message
Delay_Resp message
containing value of t4
time
t
1
t
2m
t
3m
t
4
t
1
, t
2
, t
3
, t
4
t
2
t
1
, t
2
t
3
t
2
t
1
, t
2
, t
3
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