STMicroelectronics STM3210E-EVAL, User Manual

Page: 14 / 48

Hardware layout and configuration UM0488
14/48 Doc ID 14220 Rev 5
2.18 SRAM
512Kx16 SRAM is connected to bank1 NOR/PSRAM3 of the FSMC interface and both 8-bit
and 16-bit access are allowed by BLN0 and BLN1 connected to BLE and BHE of SRAM
respectively.
2.19 NAND Flash
The 512 Mbit x8 or 1 Gbit x8 NAND Flash is connected to bank2 of the FSMC interface. The
ready/busy signal can be connected to either WAIT signal or FSMC_INT2 signal of the
STM32F103ZGT6 depending on the setting of JP7.
19 PD15 FSMC_D13
20 PD16 FSMC_D14
21 PD17 FSMC_D15
22 BL_GND GND
23 BL_control 3.3V
24 VDD 3.3V
25 VCI 3.3V
26 GND GND
27 GND GND
28 BL_VDD 3.3V
29 SDO PA6 via JP26
30 SDI PA7 via JP27
Table 12. LCD modules (continued)
TFT LCD CN16 (default) Graphic LCD U18 (optional)
Pin on
CN16
Description Pin connection
Pin on
U18
Description Pin connection
Table 13. NAND Flash related jumpers
Jumper Description
JP7
The ready/busy signal is connected to WAIT signal when JP7 is set as
shown (default setting)
The ready/busy signal is connected to FSMC_INT2 signal when JP7 is
set as shown.
1 2 3
1 2 3
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