STMicroelectronics SPEAr300, Reference Manual

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RM0082 BS_System controller
Doc ID 018672 Rev 1 293/844
14.4.2 Register description
14.4.3 SCCTRL register
The SCCTRL (control) is a RW register which is used to define the required operation of the
system controller. The SCCTRL bit assignments are given in
Table 233 .
SCPeriphID0 0xFE0 8 RO 8’h10
Peripheral identification
SCPeriphID1 0xFE4 8 RO 8’h18
SCPeriphID2 0xFE8 8 RO 8’h04
SCPeriphID3 0xFEC 8 RO 8’h00
SCPCellID0 0xFF0 8 RO 8’h0D
Identification Registes
SCPCellID1 0xFF4 8 RO 8’hF0
SCPCellID2 0xFF8 8 RO 8’h05
SCPCellID3 0xFFC 8 RO 8’hB1
Table 232. System controller identification registers summary (continued)
Name Offset Width[bit] Type Reset Value Description
Table 233. SCCTRL register bit assignments
Bit Name
Reset
value
Description
[31:24] Reserved - Read: undefined. Write: should be zero
[23] WDogEnOv 1’h0
Watchdog enable override
This bit allows to control the watchdog enable output
signal (
Section 14.3.6 ), according to the encoding:
1‘b0 = Derived from REFCLK clock source, as
defined in
Section 14.3.6
1‘b1 = Forced high
[22:21] Reserved - Read: undefined. Write: should be zero
[20] TimerEn2Ov 1’h0 Timer enable 2, override
[19] TimerEn2Sel 1’h0 Timer enable 2, timing reference select
[18] TimerEn1Ov 1’h0
Timer enable 1, override
If set, this bit forces high the timer enable output
signal. Otherwise (bit cleared), the enable output
signal follows the rules defined in
Section 14.3.6
[17] TimerEn1Sel 1’h0
Timer enable 1, timing reference select
This bit allows to select the reference clock for the
timer enable signals (
Section 14.3.6 ), according to
the encoding:
1‘b0 = REFCLK
1‘b1 = TIMCLK
[16] TimerEn0Ov 1’h0 Timer enable 0, override