RM0082
BS_System controller
Doc ID 018672 Rev 1
291/844
14.3.3
Interrupt response mode
To enable the best possible response to interrupts, the present mode bits can be override in
the system control register after an interrupt has been generated. This enables, for example,
the state machine to move from the DOZE to the NORMAL mode after an interrupt.
The interrupt response functionality is controlled by the interrupt mode control register
(SCIMCTRL,
), which defines if the functionality has been enabled, the mode
of operation that is required following an interrupt, what type of interrupt is permitted to
enable the interrupt response mode, an interrupt mode status bit and clear mechanism.
Note:
It is not possible for the interrupt response mode to slow the system operating speed, for
example, changing mode from NORMAL to SLOW.
The interrupt response mode is cleared by writing a 1‘b0 to the interrupt mode control
register SCIMCTRL. Following a power-on reset, the interrupt response mode is disabled.
14.3.4 Reset
control
The reset control is used to request a soft reset to be generated by asserting the
SOFTRESREQ output for a single SCLK cycle when any value is written to the reset status
register.
14.3.5 Core
clock
control
To enable the software to control the relative frequency of the core clock (CLK) and the bus
clock (HCLK), the system controller provides access to the HCLKDIVSEL[2:0] output
through the system control register (namely the 3 bit field HCLKDivSel of the SCCTRL
register,
).
These output signals are intended for use by the clock generation logic to control the
generation of the CLK/HCLK clock source and the HCLKEN input. To prevent spurious
change of the CLK/HCLK clock ratio, the HCLKDIVSEL output is only allowed to change
when the system mode control state machine is in a stable state, that is, the actual system
mode matches the required system mode.
14.3.6
Watchdog module clock enable generation
Enable signals are generated by the system controller to allow the watchdog module to be
clocked at a rate that is independent of the system clock
SCLK
. In particular, the enable
signals are generated by sampling a free-running, constant frequency input clock and
generating an active high pulse for a single SCLK clock cycle on each rising edge of the
input clock.
The supported module enable signals are:
●
WDCLKEN for the watchdog module clock enable.
The enable signal for the watchdog module is generated from the REFCLK input, as defined
in the system control register (SCCTRL,
Additionally, to enable the watchdog module to be clocked directly at the system clock rate, it
is also possible to selectively force the enable outputs high. The watchdog clock enable
output can be forced inactive by deasserting the WDEN input (for example, the WDEN input
can be used to disable the watchdog timer when the processor core is in a debug state).
