MACH16
S
LIM
L
ITE
3Gbps
SATA
S
TANDARD
S
OLID
-S
TATE
D
RIVE
P
ART
N
UMBER
:
M16SD2S(3)-
XXX
U(T)(X)-XXX
D
OCUMENT
N
UMBER
:
61000-07132-311
R
EVISION
N
UMBER
:
3.11
R
EVISION
D
ATE
:
01/15/2013
42
H
OST
P
OWER
F
AIL
D
ETECTION
It is possible to boost the I/O performance of the SSD by enabling the write c
ache; however, a “Flush-
Cache-to-
Flash” event implementation is necessary to prevent data loss on a sudden or ungraceful power
down. A monitor circuit using a control signal is used to flush the contents of the write cache to the flash.
The host system provides the actual trigger signal and backup power.
n
PF
S
IGNAL
The host system must generate the control signal
n
PF (Low True Power-Fail) upon detection of a power
failure. The
n
PF signal is interfaced to Pin P13 (Power Segment). The signal may be open drain or pulled
up to 3.3V, 5V or 12V. The signal should be pulled low to digital ground when asserted. See
under
. See Figure 16.
Figure 16:
n
PF Signal Interface
The host provides the active
n
PF low trigger to the SSD controller via Pin P13 to initiate the flush-cache-
to-flash power down sequence. An external power supply or host power supply will provide the backup
power for the SSD during a power loss. The power supply, interfaced with the
n
PF signal, will allow the
drive the hold-up time and power required to close the open tables and to safely flush the write cache.
The host must ensure that the power supply is fully charged
prior to asserting the
n
PF signal. A current surge limit should
be implemented for charging and to prevent reverse current
flow from the charging unit into the failing system power
supply rails.
