ST STEVAL-ISF003V1, User Manual

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Demonstration board overview UM2076
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
Allowed DC output capacitor (or DC bus capacitor): up to 2 mF. This value is the
equivalent of all capacitors in parallel at the bridge output, like C3 and C
PFC
at the PFC
in the figure below. If an interleaved PFC is used, all the output capacitors of each
PFC must be added.
Figure 3: Connection of a PFC at the HVDC output
1.6 Performance characteristics

Efficiency at 230 V 50 Hz 3.3 kW (with output DC resistive load @ COUT = 1mF) >
98%

Efficiency at 120 V 60 Hz 3.3 kW (with output DC resistive load @ COUT = 1mF) > 98
%

Standby losses < 300 mW (see Section 3.7: "Standby consumption" )

Compliance with IEC 61000-3-3 (with MAX_INRUSH CURRENT potentiometer set to
default position, see
Section 7: "Inrush-current limitation" )

Compliance with EN55014 (CIPSPR 22 method B, see Section 11: "EN55014 test
results" )

IEC 61000-4-4: 2 kV criteria A, SCR1 and SCR2 withstands a level of 5 kV without
triggering. This avoids undesired triggering and uncontrolled inrush current in case of
EMI noise.

IEC 61000-4-5: 4 kV

IEC61000-4-11: criteria A for dips down to 100% of the line voltage during 1 cycle;
criteria B for interrupts up to 300 cycles or more (see
Section 8: "Mains voltage dips
and interruptions" ).
The figure below shows an example of the progressive DC capacitor charge which is
ensured by SCR1 and SCR2. The test is performed at start-up when the STEVAL-
ISF003V1 board is connected to a 230 V, 50 Hz grid (V
AC
), while the output DC capacitor is