ST STEVAL-ISF003V1, User Manual

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UM2076 Getting started
DocID029457 Rev 1 15/43
output capacitor is charged. This signal is referenced to GND_DC terminal and is available
from the J16 header.
The PFC_START signal is an open drain output that must be compatible with the digital rail
used by an external system. The PFC DC storage capacitor (C
PFC
in Figure 3: "Connection
of a PFC at the HVDC output" ) must be inside the range specified in Section 3.5:
"Operating range " .
Connector J13 gives the rectifier AC line voltage and can be used to by an
external PFC to shape the input current waveform.
Figure 10: PFC activation permission (PFC_Start signal) when the HV output capacitor is
charged
2.5.3 Motor inverter connection
An inverter or any other DC/DC power converter can be added after the PFC or directly
behind the HVDC bus output.
A 15 V positive output referenced to the DC Bus Ground (GND_DC) is available on header
J11 to supply an IPM module if needed. The maximum current sunk from this supply must
be well below the limit in .
2.5.4 Control with an external microcontroller
You can control the STEVAL-ISF003V1 front-end circuit with an external MCU instead of
the embedded STM8S003F3 MCU to directly check the compliance of your own firmware
with this kind of circuit.
All the control signals required to drive the SCRs are available on the J16 header.
EC_SCR1 and EC_SCR2 are the connections to externally drive SCR1 and SCR2,
respectively. GND_DC of the DC bus ground and the ZVS_ext signal (to synchronize the
control signals of the external MCU) are also available on this header.