background image

SPBT2632C2A

Hardware specifications

Doc ID 022833 Rev 4

11/27

5.3 

High speed CPU mode current consumption

High speed CPU mode

CPU 32 MHz

UART supports up to 921 Kbps

Data throughput up to 1.5 Mbps

Shallow sleep enabled.

5.4 

Standard CPU mode current consumption

Standard CPU mode

CPU  8  MHz

UART supports up to 115 Kbps

Data throughput up to 200 Kbps

Shallow sleep enabled.

Table 3.

High speed CPU mode current consumption

Modes

 

(typical power consumption)

        Avg.

    Unit

ACL data 115 K baud UART at max. throughput (master)

23

mA

ACL data 115 K baud UART at max. throughput (slave)

27.5

mA

Connection, no data traffic, master

9.1

mA

Connection, no data traffic, slave

11.2

mA

Connection 375 ms sniff (external LPO required) 

490

µA

Standby, without deep sleep

8.6

mA

Standby, with deep sleep, no external LPO

1.7

mA

Standby, with deep sleep, with external LPO

70

µA

Page/inquiry scan, with deep sleep, no external LPO

2.7

mA

Page/inquiry scan, with deep sleep, with external LPO

520

µA

Bluetooth power down / CPU standby, no external LPO

25

µA

Table 4.

Standard CPU mode current consumption

Modes

 

(typical power consumption)

        Avg.

    Unit

ACL data 115 K baud UART at max. throughput (master)

16.7

mA

ACL data 115 K baud UART at max. throughput (slave)

18

mA

Connection, no data traffic, master

4.9

mA

Connection, no data traffic, slave

7.0

mA

Connection 375 ms sniff (external LPO required) 

490

µA

Standby, without deep sleep

4.2

mA

Standby, with deep sleep, no external LPO

1.7

mA

Summary of Contents for SPBT2632C2A

Page 1: ...tenna Multipoint capability ST micro Cortex M3 microprocessor up to 72 MHz Memory 256 kb Flash memory 48 kb RAM memory Data rate 1 5 Mbps maximum data rate Serial interface UART up to 2 0 Mbps SPI int...

Page 2: ...conditions 10 5 2 Absolute maximum ratings 10 5 3 High speed CPU mode current consumption 11 5 4 Standard CPU mode current consumption 11 5 5 I O operating characteristics 12 5 6 Selected RF characte...

Page 3: ...SPBT2632C2A Contents Doc ID 022833 Rev 4 3 27 7 6 External LPO input circuit 20 7 7 Apple iOS CP reference design 21 8 Regulatory compliance 23 9 Ordering information 25 10 Revision history 26...

Page 4: ...10 Table 3 High speed CPU mode current consumption 11 Table 4 Standard CPU mode current consumption 11 Table 5 I O operating characteristics 12 Table 6 Selected RF characteristics 12 Table 7 Pin assi...

Page 5: ...SPBT2632C2A AT2 module block diagram 15 Figure 5 Soldering profile 17 Figure 6 Connection to host device 17 Figure 7 Typical RS232 circuit 18 Figure 8 PCB layout guidelines 18 Figure 9 External reset...

Page 6: ...emory contains embedded firmware for serial cable replacement using the Bluetooth SPP profile Embedded Bluetooth AT2 command firmware is a friendly interface which realizes a simple control for cable...

Page 7: ...2 RoHS compliance ST modules are RoHS compliant and comply with ECOPACK norms 3 Applications Serial cable replacement M2M industrial control Service diagnostic Data acquisition equipment Machine cont...

Page 8: ...fully supported to maximum allowed intervals Master slave switch supported during connection and post connection Dedicated inquiry access code for improved inquiry scan performance Dynamic packet sel...

Page 9: ...SPBT2632C2A Software architecture Doc ID 022833 Rev 4 9 27 4 4 Bluetooth firmware implementation Figure 1 FW architecture V I 0...

Page 10: ...mum ratings Table 1 Recommended operating conditions Rating Min Typical Max Unit Operating temperature range 40 85 C Supply voltage VIN 2 1 2 5 3 6 V Signal pin voltage 2 1 V RF frequency 2400 2483 5...

Page 11: ...1 mA Connection no data traffic slave 11 2 mA Connection 375 ms sniff external LPO required 490 A Standby without deep sleep 8 6 mA Standby with deep sleep no external LPO 1 7 mA Standby with deep sle...

Page 12: ...H High level input voltage 1 4 V VIN 2 1 V VOL Low level output voltage 0 4 V VIN 2 1 V VOH High level output voltage 1 8 V VIN 2 1 V IOL Low level output current 4 0 mA VOL 0 4 V IOH High level outpu...

Page 13: ...ctive low ADC 0 I2 C clock aux UART Rx Y CTS I 11 Clear to send active low ADC 1 I2 C data aux UART Tx Y Boot loader Boot 0 I 9 Boot 0 Power and ground Vin 8 Vin GND 7 GND Reset RESETN I 10 Reset inpu...

Page 14: ...Hardware specifications SPBT2632C2A 14 27 Doc ID 022833 Rev 4 5 8 Pin placement Figure 2 Pin placement 5 9 Layout drawing Figure 3 Layout drawing V MILLIMETERS 3IZE MM X MM X MM HEIGHT TOLERANCE MM V...

Page 15: ...diagram Doc ID 022833 Rev 4 15 27 6 Hardware block diagram Figure 4 SPBT2632C2A AT2 module block diagram DWWHU RU 6XSSO 5HJXODWRU QWHQQD RVW RQWUROOHU QWHUIDFH 67 3 LOWHU 32 ORFN 6 3 0 ODVK 5 0 8 57...

Page 16: ...e reflow installation The SPB2632C2A is a surface mount Bluetooth module supplied on a 16 pin 6 layer PCB The final assembly recommended reflow profiles are indicated here below The soldering phase mu...

Page 17: ...current GPIO 1 to GPIO 7 are internally pulled down with 100 k nominal resistors 7 3 UART interface The UART is compatible with the 16550 industry standard Four signals are provided with the UART int...

Page 18: ...Hardware design SPBT2632C2A 18 27 Doc ID 022833 Rev 4 Figure 7 Typical RS232 circuit 7 4 PCB layout guidelines Figure 8 PCB layout guidelines V SURROUNDING V...

Page 19: ...et circuits are detailed below 7 5 1 External reset circuit Figure 9 External reset circuit Note RPU ranges from 30 k to 50 k internally 7 5 2 Internal reset circuit Figure 10 Internal reset circuit N...

Page 20: ...ls Low 0 5 V High 1 8 V Input capacitance 2 5 pF maximum Configurations Use two configuration variables UseExtLPO and AllowSniff Figure 11 External LPO circuit Table 9 System configuration variables V...

Page 21: ...pple iOS CP reference design The figures below give an indicative overview of what the hardware concept looks like A specific MFI co processor layout is available for licensed MFI developers from the...

Page 22: ...Hardware design SPBT2632C2A 22 27 Doc ID 022833 Rev 4 Figure 14 Power switch V...

Page 23: ...e that may cause undesired operation Modifications or changes to this equipment not expressly approved by the part responsible for compliance may render void the user s authority to operate this equip...

Page 24: ...Wideband transmission systems data transmission equipment operating in the 2 4 GHZ ISM band and using wideband modulation techniques harmonized EN covering essential requirements under article 3 2 of...

Page 25: ...SPBT2632C2A Ordering information Doc ID 022833 Rev 4 25 27 9 Ordering information Table 10 Ordering information Order code Description SPBT2632C2A AT2 Class 2 OEM Bluetooth antenna module...

Page 26: ...able 11 Document revision history Date Revision Changes 03 Apr 2012 1 First release 16 Apr 2012 2 Modified Section 8 12 Jun 2012 3 Document status promoted from preliminary data to production data Mod...

Page 27: ...WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UN...

Reviews: