ST M95010-125 User Manual Download Page 1

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January 2012

Doc ID 022545 Rev 1

1/36

M95040-125

M95020-125 M95010-125

Automotive 4-Kbit, 2-Kbit and 1-Kbit SPI bus EEPROM

Features

■

Compatible with the Serial Peripheral Interface
(SPI) bus

■

Memory array

– 1 Kbit, 2 Kbit or 4 Kbit of EEPROM

– Page size: 16 bytes

– Write protection by block: 1/4, 1/2 or whole

memory

■

5 MHz clock frequency

■

Write cycle within 5 ms

■

Operating temperature range: -40 °C to
+125 °C

■

Single supply voltage:

– 4.5 V to 5.5 V for M950x0

– 2.5 V to 5.5 V for M950x0-W

■

More than 1 million Write cycles

■

More than 40-year data retention

■

Enhanced ESD protection

■

Packages

– RoHS-compliant and halogen-free

(ECOPACK2

)

SO8 (MN)

150 mil width

TSSOP8 (DW)

169 mil width

www.st.com

Obsolete Product(s) - Obsolete Product(s)

Summary of Contents for M95010-125

Page 1: ...tes Write protection by block 1 4 1 2 or whole memory 5 MHz clock frequency Write cycle within 5 ms Operating temperature range 40 C to 125 C Single supply voltage 4 5 V to 5 5 V for M950x0 2 5 V to 5...

Page 2: ...9 Supply voltage VCC 9 2 9 1 Operating supply voltage VCC 9 2 9 2 Device reset 9 2 9 3 Power up conditions 10 2 9 4 Power down 10 3 Connecting to the SPI bus 11 3 1 SPI modes 12 4 Operating features...

Page 3: ...R 20 6 5 Read from Memory Array READ 21 6 6 Write to Memory Array WRITE 22 7 Power up and delivery states 24 7 1 Power up state 24 7 2 Initial delivery state 24 8 Maximum rating 25 9 DC and AC paramet...

Page 4: ...grade 3 26 Table 9 AC test measurement conditions 26 Table 10 Capacitance 27 Table 11 DC characteristics M950x0 device grade 3 27 Table 12 DC characteristics M950x0 W device grade 3 27 Table 13 AC cha...

Page 5: ...RDI sequence 17 Figure 9 Read Status Register RDSR sequence 19 Figure 10 Write Status Register WRSR sequence 20 Figure 11 Read from Memory Array READ sequence 21 Figure 12 Byte Write WRITE sequence 22...

Page 6: ...s can operate with supply voltages ranging from 2 5 V to 5 5 V The devices are guaranteed over the 40 C 125 C temperature range and are compliant with the Automotive standard AEC Q100 Grade 1 Figure 1...

Page 7: ...iption Doc ID 022545 Rev 1 7 36 Table 1 Signal names Signal name Function C Serial Clock D Serial Data input Q Serial Data output S Chip Select W Write Protect HOLD Hold VCC Supply voltage VSS Ground...

Page 8: ...es the timing of the serial interface Instructions addresses or data present at Serial Data Input D are latched on the rising edge of Serial Clock C Data on Serial Data Output Q changes after the fall...

Page 9: ...ecouple the VCC line with a suitable capacitor usually of the order of 10 nF to 100 nF close to the VCC VSS package pins 2 9 2 Device reset In order to prevent inadvertent write operations during powe...

Page 10: ...ing edge has first been detected on Chip Select S This ensures that Chip Select S must have been high prior to going low to start the first operation The VCC voltage has to rise continuously from 0 V...

Page 11: ...es are high impedance The pull up resistor R represented in Figure 3 ensures that a device is not selected if the bus master leaves the S line in the high impedance state In applications where the bus...

Page 12: ...modes input data is latched in on the rising edge of Serial Clock C and output data is available from the falling edge of Serial Clock C The difference between the two modes as shown in Figure 4 is th...

Page 13: ...t is required to reset any processes that had been in progress The Hold condition starts when the Hold HOLD signal is driven low at the same time as Serial Clock C already being low as shown in Figure...

Page 14: ...S must be driven high after the rising edge of Serial Clock C that latches the last bit of the instruction and before the next rising edge of Serial Clock C For this the last bit of the instruction c...

Page 15: ...e memory is organized as shown in Figure 6 Figure 6 Block diagram AI01272d HOLD S W Control logic High voltage generator I O shift register Address register and counter Data register 1 page X decoder...

Page 16: ...bits of the instruction byte are shifted in on Serial Data Input D The device then enters a wait state It waits for a the device to be deselected by Chip Select S being driven high Figure 7 Write Ena...

Page 17: ...ruction byte are shifted in on Serial Data Input D The device then enters a wait state It waits for a the device to be deselected by Chip Select S being driven high The Write Enable Latch WEL bit in f...

Page 18: ...Write Enable Latch WEL Write In Progress WIP are dynamically updated during the ongoing Write cycle Bits b7 b6 b5 and b4 are always read as 1 The status and control bits of the Status register are as...

Page 19: ...Rev 1 19 36 Figure 9 Read Status Register RDSR sequence C D S 2 1 3 4 5 6 7 8 9 10 11 12 13 14 15 Instruction 0 AI01444D Q 7 6 5 4 3 2 1 0 Status Register Out High Impedance MSB 7 6 5 4 3 2 1 0 Statu...

Page 20: ...s WIP bit the WIP bit is 1 during the self timed write cycle tW and 0 when the write cycle is complete The WEL bit Write enable latch is also reset at the end of the write cycle tW The Write Status Re...

Page 21: ...ddress is reached the address counter rolls over to zero allowing the Read cycle to be continued indefinitely The whole memory can therefore be read with a single READ instruction The Read cycle is te...

Page 22: ...tinues to be driven low the next byte of input data is shifted in and used to overwrite the byte at the start of the current page The instruction is not accepted and is not executed under the followin...

Page 23: ...its are Don t Care C D S 2 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Instruction Byte Address 0 Data Byte 1 C D AI01443D S 26 25 27 28 29 30 31 8 8N 24 Data Byte 16 9 8N 10 8N 11 8N 12...

Page 24: ...quired on Chip Select S before any instructions can be started not in the Hold Condition the Write Enable Latch WEL is reset to 0 Write In Progress WIP is reset to 0 The BP1 and BP0 bits of the Status...

Page 25: ...nit Ambient operating temperature 40 130 C TSTG Storage temperature 65 150 C TLEAD Lead temperature during soldering see note 1 1 Compliant with JEDEC Std J STD 020 for small body Sn Pb or Pb assembly...

Page 26: ...quoted parameters Figure 14 AC test measurement I O waveform Table 7 Operating conditions M950x0 device grade 3 Symbol Parameter Min Max Unit VCC Supply voltage 4 5 5 5 V TA Ambient operating temperat...

Page 27: ...3 VCC V VIH Input high voltage 0 7 VCC VCC 1 V VOL Output low voltage IOL 2 mA VCC 5 V 0 4 V VOH Output high voltage IOH 2 mA VCC 5 V 0 8 VCC V VRES 1 1 Characterized only not tested in production Int...

Page 28: ...tCLL Clock low time 90 ns tCLCH 2 2 Characterized only not tested in production tRC Clock rise time 1 s tCHCL 2 tFC Clock fall time 1 s tDVCH tDSU Data in setup time 20 ns tCHDX tDH Data in hold time...

Page 29: ...1 tCLL Clock low time 90 ns tCLCH 2 2 Characterized only not tested in production tRC Clock rise time 1 s tCHCL 2 tFC Clock fall time 1 s tDVCH tDSU Data in setup time 20 ns tCHDX tDH Data in hold tim...

Page 30: ...022545 Rev 1 Figure 15 Serial input timing Figure 16 Hold timing C D AI01447d S MSB IN Q tDVCH High impedance LSB IN tSLCH tCHDX tCLCH tSHCH tSHSL tCHSH tCHSL tCH tCL tCHCL C Q AI01448c S HOLD tCLHL t...

Page 31: ...125 M95010 125 DC and AC parameters Doc ID 022545 Rev 1 31 36 Figure 17 Serial output timing C Q AI01449f S D ADDR LSB IN tSHQZ tCH tCL tQLQH tQHQL tCHCL tCLQX tCLQV tSHSL tCLCH Obsolete Product s Ob...

Page 32: ...outline 1 Drawing is not to scale Table 15 SO8N 8 lead plastic small outline 150 mils body width package mechanical data Symbol millimeters inches 1 1 Values in inches are converted from mm and round...

Page 33: ...are converted from mm and rounded to 4 decimal digits Typ Min Max Typ Min Max A 1 2 0 0472 A1 0 05 0 15 0 002 0 0059 A2 1 0 8 1 05 0 0394 0 0315 0 0413 b 0 19 0 3 0 0075 0 0118 c 0 09 0 2 0 0035 0 007...

Page 34: ...pe M95 SPI serial access EEPROM Device function 040 4 Kbit 512 x 8 020 2 Kbit 256 x 8 010 1 Kbit 128 x 8 Operating voltage blank VCC 4 5 to 5 5V W VCC 2 5 to 5 5V Package MN SO8 150 mil width DW TSSOP...

Page 35: ...M95020 125 M95010 125 Revision history Doc ID 022545 Rev 1 35 36 12 Revision history Table 18 Document revision history Date Version Changes 02 Jan 2012 1 Initial release Obsolete Product s Obsolete...

Page 36: ...ES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS EXPR...

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