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Application

M41T00AUD

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3 Application

Figure 3.

Application diagram

AU TOMATIC

BATTERY

SWITCHOVER

& DESELEC T

VCC

2

I2C

VCC

32KHz

OSCILL ATOR

400kHz I2C

INTER FACE

OSCI

OSCO

uC

REFERENCE

VPFD=2.80V

IRQ/FT/OUT

TRICKLE

CHARGE

VINT

VBACK

VCC

256/512Hz

AUDIO

BPF

ADJ

GAIN

AIN

AOUT+
AOUT–

VSS

VBIAS

WRITE

FBK

Audio-in

M41T00AUD

ai13324

SECS

MINS

HOURS

DATE

DAY

MONTH

YEAR

CENTURY BIT
CALIBRATION

OUT

OSCILLATOR

FAIL DETECT

I2C
(SDA,
SCL)

PROTECT

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7
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9
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Summary of Contents for M41T00AUD

Page 1: ...ode RTC operates using 32 768Hz quartz crystal Calibration register provides for adjustments of 63 to 126ppm Oscillator supports crystals with up to 40k series resistance 12 5pF load capacitance Oscil...

Page 2: ...5 M41T00AUD clock operation 16 5 1 Clock registers 16 5 1 1 Halt bit operation 17 5 1 2 Oscillator fail detect operation 17 5 1 3 Trickle charger 17 5 2 Reading and writing the clock registers 18 5 3...

Page 3: ...M41T00AUD Contents 3 44 8 Initial conditions 33 9 Maximum ratings 34 10 DC and AC parameters 35 11 Package mechanical data 39 12 Part numbering 42 13 Revision history 43...

Page 4: ...aximum ratings 34 Table 10 Operating and AC measurement conditions 35 Table 11 Input output characteristics 25 C f 1MHz 35 Table 12 DC characteristics 36 Table 13 Crystal electrical characteristics 36...

Page 5: ...sequence 12 Figure 8 Slave address location 14 Figure 9 READ mode sequence 14 Figure 10 Alternate READ mode sequence 14 Figure 11 WRITE mode sequence 15 Figure 12 Counter update diagram 20 Figure 13 S...

Page 6: ...up input when VCC is removed Backup power can be supplied by a capacitor or by a battery such as a Lithium coin cell The device includes a trickle charge circuit for charging the capacitor The RTC inc...

Page 7: ...OSCI Oscillator input OSCO Oscillator output SCL I2 C serial clock SDA I2 C serial data AIN Audio input VBIAS Input for decoupling capacitor VSS Ground AOUT Analog out 180 phase AOUT Analog out 0 phas...

Page 8: ...2C VCC 32KHz OSCILLATOR 400kHz I2C INTERFACE OSCI OSCO uC REFERENCE VPFD 2 80V IRQ FT OUT TRICKLE CHARGE VINT VBACK VCC 256 512Hz AUDIO BPF ADJ GAIN AIN AOUT AOUT VSS VBIAS WRITE FBK Audio in M41T00AU...

Page 9: ...SCL SDA 4 7k 3 3V 1 2 32 768kHz 6 typical Lithium Cell Battery alternative Either or but not both 5 Optional connection to micro 13 16 8 or higher 11 R1x 20k R1x 20k Optional can sum additional audio...

Page 10: ...puts to the device will not be recognized at this time to prevent erroneous data from being written to the device from an out of tolerance system When VCC falls below VSO the device automatically swit...

Page 11: ...ed with a start condition and terminated with a stop condition The number of data bytes transferred between the start and stop conditions is not limited The information is transmitted byte wide and ea...

Page 12: ...1 P STOP and S START AI00587 DATA CLOCK DATA LINE STABLE DATA VALID START CONDITION CHANGE OF DATA ALLOWED STOP CONDITION AI00601 DATA OUTPUT BY RECEIVER DATA OUTPUT BY TRANSMITTER SCLK FROM MASTER ST...

Page 13: ...ll continue until the master receiver sends a STOP condition to the slave transmitter An alternate READ mode may also be implemented whereby the master reads the M41T00AUD slave without first writing...

Page 14: ...ADDRESS START A 0 1 0 0 0 1 1 MSB LSB AI00899 BUS ACTIVITY ACK S ACK ACK ACK NO ACK STOP START P SDA LINE BUS ACTIVITY MASTER R W DATA n DATA n 1 DATA n X WORD ADDRESS An SLAVE ADDRESS S START R W SLA...

Page 15: ...n within the device on the reception of an acknowledge clock The M41T00AUD slave receiver will send an acknowledge clock to the master transmitter after it has received the slave address and again aft...

Page 16: ...Century Hours Register contain the hours in BCD format with values in the range 0 to 23 Bits D7 and D6 contain the century enable bit CEB and the century bit CB CB provides a one bit indicator for th...

Page 17: ...tion to the HT bit getting set to 1 automatically at power down the user can also write it to 1 to halt updating of the registers 5 1 2 Oscillator fail detect operation Bits D5 and D4 of register 09 h...

Page 18: ...tes are suspended Timekeeping continues but the registers are frozen until after a STOP condition or a non RTC register 07h to 09h is read Suspending the updates ensures that a clock roll over does no...

Page 19: ...FT S Calibration Cal control 08h 256 512 TONE TCH2 MUTE GAIN Audio 09h HT TCFE OF OFIE TCHE3 TCHE2 TCHE1 TCHE0 Control2 1 Key S SIGN bit FT Frequency Test bit ST STOP bit OF Oscillator Fail Detect Fla...

Page 20: ...OUNTER DIVIDE BY 1 Hz SECONDS MINUTES HOURS MONTHS YEARS CENTURIES COUNTER COUNTER COUNTER COUNTER COUNTER COUNTER REGISTER REGISTER REGISTER REGISTER DAY DATE REGISTER REGISTER REGISTER READ WRITE BU...

Page 21: ...n is an interrupt output which will be asserted anytime the OF bit D5 of register 09h goes true See Section 5 for more details During calibration the pin can be used as a frequency test output When FT...

Page 22: ...VCC as long as possible before switching to the backup supply As shown in Figure 13 whenever VBACK is greater than VPFD switchover occurs when VCC drops below VPFD Conversely when VBACK is less than V...

Page 23: ...tches open as well The application must close them after power up to re enable the trickle charge function The use of two switches in the chain is to protect against accidental unwanted charging as mi...

Page 24: ...on symmetric calibration scheme Positive values for speeding the clock up have more effect than negative values for slowing it down A positive value will speed the clock up by approximately 4ppm per s...

Page 25: ...libration step has an effect on clock accuracy of either 4 068 or 2 034 ppm Assuming that the oscillator is running at exactly 32 768Hz each of the 31 steps in the calibration byte would represent sub...

Page 26: ...pm 33 ppm 9 01001 18 ppm 37 ppm 10 01010 20 ppm 41 ppm 11 01011 22 ppm 45 ppm 12 01100 24 ppm 49 ppm 13 01101 26 ppm 53 ppm 14 01110 28 ppm 57 ppm 15 01111 31 ppm 61 ppm 16 10000 33 ppm 65 ppm 17 1000...

Page 27: ...ation 27 44 Figure 15 Crystal accuracy across temperature AI00999b 160 0 10 20 30 40 50 60 70 Frequency ppm Temperature C 80 10 20 30 40 100 120 140 40 60 80 20 0 20 DF K x T TO 2 K 0 036 ppm C2 0 006...

Page 28: ...ith that and 20k input resistors the input signals will be summed at unity gain An audio switch follows the amplifier A tone selectable between 256 and 512 Hz can be inserted into the audio stream in...

Page 29: ...e input Switch 256 512 signal in place of audio signal GAIN 3dB steps 33dB to 12dB 4 bit register 300mW 8 V DD V DD 2 V DD 2 V BIAS AOUT AOUT AIN Low end of band pass filter is actually implemented by...

Page 30: ...N values of E B 5 and 4 MUTE GAIN Audio gain dB AV scalar gain Binary Hex Min Typ Max Typ 1 XXXX X Off Off 0 1111 F 12 4 0 1110 E 7 9 11 2 8 0 1101 D 6 2 0 1100 C 3 1 4 0 1011 B 1 0 1 1 0 1010 A 3 0 7...

Page 31: ...IN AOUT is measured between the output pins AOUT and AOUT AOUT AOUT AOUT Each of the output levels is determined by the ratio of the feedback and input resistors along with the GAIN value AOUT SIN x A...

Page 32: ...This applies to all steps except the lowest one from GAIN 0 to GAIN 1 which is not tested In summary for GAIN 1 to GAIN Fh all steps are tested to have a 1dB step size tolerance of the listed 3dB ste...

Page 33: ...always turned completely off after any power up The bits affecting it are set to levels which keep all the trickle charge switches open Both TCH2 and TCFE are 0 which opens their corresponding switch...

Page 34: ...her relevant quality documents Caution Negative undershoots below 0 3V are not allowed on any pin while in the back up mode Table 9 Absolute maximum ratings Symbol Parameter Value Unit TSTG Storage te...

Page 35: ...tions 1 1 Output Hi Z is defined as the point where data is no longer driven Parameter M41T00AUD Supply voltage VCC 3 0 to 3 6V Ambient operating temperature TA 0 to 70 C Digital load capacitance CL 1...

Page 36: ...BACK 3V 0 6 1 A 1 Valid for ambient operating temperature TA 0 to 70 C VCC 3 0 to 3 6V except where otherwise noted 2 For open drain pins IRQ FT OUT and SDA 3 STMicroelectronics recommends the RAYOVAC...

Page 37: ...DA at VIH before power down 0 ns trec SCL and SDA at VIH after power up 10 s Table 15 RTC power down up trip points DC characteristics Symbol Parameter 1 2 1 All voltages referenced to VSS 2 Valid for...

Page 38: ...Typ Max Unit VOO Output offset voltage No input signal RL 8 10 100 mV PO MAX Maximum output power THD 2 Max f 1kHz RL 8 300 375 mW PSRR Power supply rejection ratio RL 8 Av 2 VRIPPLE 200mVPP audio in...

Page 39: ...se packages have a lead free second level interconnect The category of second level interconnect is marked on the package and on the inner box label in compliance with JEDEC Standard JESD97 The maximu...

Page 40: ...Package mechanical data M41T00AUD 40 44 Figure 19 DFN16 5mm x 4mm package outline 1 Drawing is not to scale DFN16_ME BTM VIEW E2 D2 SEATING A PLANE SIDE VIEW A1 A3 C e e b L PIN 1 D E...

Page 41: ...Min Typ Max Min Typ Max A 0 80 0 90 1 00 0 032 0 035 0 040 A1 0 00 0 02 0 05 0 00 0 0007 0 002 A3 0 20 0 008 b 0 20 0 25 0 30 0 008 0 010 0 012 D 5 00 0 197 E 4 00 0 157 D2 4 20 4 35 4 45 0 165 0 171...

Page 42: ...mbering Table 18 Ordering information scheme Example M41T00AUD D 1 F Device type M41T00AUD Package D Lead free 5mm x 4mm DFN Temperature range 1 0 C to 70 C Shipping method E ECOPACK lead free ICs in...

Page 43: ...1T00AUD Revision history 43 44 13 Revision history Table 19 Document revision history Date Revision Changes 01 May 2007 1 Initial release 13 Dec 2007 2 Minor text changes updated footnote 1 in Table 1...

Page 44: ...RANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS...

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