Operation
M41T00AUD
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4 Operation
The M41T00AUD clock operates as a slave device on the serial bus. Access is obtained by
implementing a start condition followed by the correct slave address (D0h). The 10 bytes
contained in the device can then be accessed sequentially in the following order:
The M41T00AUD continually monitors V
CC
for an out of tolerance condition. Should V
CC
fall
below V
PFD
, the device terminates an access in progress and resets the device address
counter. Inputs to the device will not be recognized at this time to prevent erroneous data
from being written to the device from an out of tolerance system. When V
CC
falls below V
SO
,
the device automatically switches over to the backup battery or capacitor and powers down
into an ultra low current mode of operation to conserve battery life. Upon power-up, the
device switches from battery to V
CC
at V
SO
and recognizes inputs.
Table 2.
List of registers
Byte address
Contents
00h
Seconds register
01h
Minutes register
02h
Century/hours register
03h
Day register
04h
Date register
05h
Month register
06h
Years register
07h
Calibration/control register
08h
Audio register
09h
Control2 register
