SRS Labs SR640 Series, Manual

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16
I NTRODUCTI ON
Schematics for the SR640 series dual-
channel filters are shown on the following
pages. They include the following: Pream-
plifier, filter stage, output amplifier, op-
toisolated interface, microprocessor sec-
tion, communications section, front panel
interface, power supplies, and front panel.
The preamplifer, filter stages (4/channel),
output amplifer, and optoisolated inter-
face are located on the individual filter
boards (2/instrument). The microprocessor
and commuinication components are locat-
ed on the digital board at the rear of the
instrument.
Pr eampl i fi er
The preamplifier is a low-noise fully dif-
ferential amplifier with gains from 0 to
60 db. Relays K1 and K2 select the input
source and coupling, while K4 switches in
a X10 attenuator used at the three lowest
gain settings. The Dual FET U2, along with
low-noise op-amps U3 and U4 form the
feedback stabilized differential pair at the
heart of the premplifier. U6 and U8 pro-
vide additional amplification. The output
of the preamplifier is switched by U9 to
the first filter stage or directly to the
output amplifier if the filter has been by-
passed.
Fi l ter Stages
Each of the four filter stages is derived
from a 3 op-amp biquadratic filter with a
low pass transfer function of:
Stage paramaters for the low pass filter
are:
1 .6347 .5493 -
2 .8060 .9507 2.0793
3 .9850 2.095 1.9653
4 1.076 7.375 2.6776
For the high pass filter, the parameters
are simply related by the lowpass to high-
pass transformation.
Component designations for the filter
stage will be refered to as UnXX where n
designates the stage number. Un14A, C,
and D form the actual filter section. The
tuning capacitors Cn20-Cn27 are switched
by relays Kn05 and Kn06 according the the
decade. Fine tuning within a decade is ac-
complished by the 10 bit parallel resistor
networks composed of Rn40 through Rn59.
Switching of the resistors is done with the
FET switches Qn00 through Qn19 and their
associated driver diodes.
The dual 8 bit DAC Un12 and its related
output op-amps along with Un13A and dif-
ferential amp Un13D allow the pole fre-
quency and Q of the circuit to be fine tuned
by adj usting the values sent to the dual
DAC. This is how the unit is calibrated.
The magnitude of the 'fine tuning' is set by
Rn60 and Rn61.
The zero frequency of the circuit is not
digitally adj ustable but is instead set by
resistors Rn71 and Rn72. Jumpers JPn05-
n07 allow the zero-forming network to be
removed from the circuit in stages that do
not have zeros. The single op-amp Un15
forms the output buffer for the stage.
Ci r cui t Descr i pti on
T (s )
=
s
2
+ ω
z
2
s
2
+
ω
p
Q
s
+ ω
p
2
Stg
ω
p
Q
ω
z
/
ω
p
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