3.5 Status Model
61
occur, the corresponding bit is set. Reading the register clears it (reading
a single bit clears only that bit). This register is also cleared by the
*CLS
command.
In addition to monitored events from the CHCR, two discrete events—a
chopper head memory failure or sudden disconnect—are directly de‑
fined in CHEV without a corresponding real‑time condition bit in the
CHCR:
Weight
Bit
Flag
32
5
Chopper Head Memory Fail
64
6
Chopper Head Disconnect
On each motor startup, the control unit reads calibration and identifica‑
tion information from the chopper head. If this memory access fails, bit
5 of the CHEV register will be set.
If the chopper head cable is not properly connected, bit 6 of the CHEV
register will be set. The chopper head cable connectivity is checked
at motor startup and monitored continuously during motor operation.
Connectivity is not monitored when the motor is off.
An example use case of CHNT and CHEV is shown in Figure 3.2. Before
the start of the example, the command
CHNT 8
is sent to latch negative
(1
→
0) transitions of the CHCR PL (Phase Locked) bit into the CHEV reg‑
ister. Note that periodic monitoring of the CHCR real‑time register may
miss a temporary loss‑of‑lock depending on the timing of the
CHCR?
query.
CHCR PL (Phase Locked)
»CHCR? 3
»CHEV?
0
1
0
0
0
0
1
0
1
0
1
8
Figure 3.2:
Phase Lock status (0 or 1) of the chopper head versus time. Nega‑
tive (1
→
0) transitions of the CHCR PL status bit can be latched into the CHEV
register by commanding
CHNT 8
. Query results for
CHCR? 3
and
CHEV?
are
shown as numeric responses at the indicated timing.
3.5.5.4
Chopper Status Enable (CHEN) Register
This is an 8‑bit wide register that masks the CHEV register. The log‑
ical OR of the bitwise AND of CHEV and CHEN produces the CHSB
message in the Status Byte register (SB).
SR542 Precision Optical Chopper
