SRS Labs QMS 100 Series, User Manual

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B-8 Description of Schematics
SRS QMS Gas Analyzer
Q2 CAL_2 MSB of current detector calibration attenuator
multiplexer.
Q3
MPX_0 LSB of 16-bit A/D converter's input multiplexer.
Q4 MPX_1 Middle bit of 16-bit A/D converter's input multiplexer.
Q5 MPX_2 MSB of 16-bit A/D converter's input multiplexer.
Q6 EMIT_CTL Filament heater duty cycle control: 0=direct, 1=regulate
Q7 GRID_SEL Low for low grid potential, high for high grid potential.
The MISC port
Q0 RF_ON Low to turn-off RF, high to turn on.
Q1 IONS_OFF Pulse high for 50ms to reset relay so that ion current goes to
gnd.
Q2
IONS_ON Pulse high to set latching relay so ion current enters I/V.
Q3 MULT_OFF Pulse high to ground e-multiplier anode.
Q4 MULT_ON Pulse high to connect e-multiplier to I/V.
Q5 LINEAR Pulse high for linear I/V converter (offset calibration).
Q6 R/-C Set high to read 16-bit A/D, low to initiate conversion.
Q6 CS_VETO Set high to prevent (or release) -CS to 16-bit A/D converter.
Clocks
The master clock of the system is an 11.0592 MHz crystal oscillator. This frequency was selected for
the following reasons:
1. It is close to the maximum operating frequency for the 68HC11 (12 MHz).
2. When divided by four it provides a usable RF frequency (2.7648 MHz).
3. When divided by 128 it provides a clock for switching power supplies (86.4 kHz).
4. When divided by 256 it provides a clock for the high voltage DC-DC converter.
5. When divided by 384 it provides an exact PC baud rate (28.8 kbaud).
6. When divided by 2
14
it provides a A/D convert rate (675 Hz).
Since the A/D convert rate is a sub-multiple of all the other system clocks, crosstalk from the clocks will
be synchronous, and will generate a fixed offset to the signal (which may be measured and subtracted)
instead of noise.
The clock division for the 28.8 kBaud rate is done by the microcontroller; the rest of the clock division
is done by U108, a 74HC4020 14-stage ripple divider. The 172.8kHz square wave is formed into a
100ns wide pulse to be used as a switching power supply sync pulse, which is divided by two by the
power supply controller. U109, a 74HC74 dual D-type flip-flop, provides the complimentary drive
required for the RF and high-voltage inverter circuits. Either of these drives may be turned off (both Q
and -Q outputs set high) by setting the control bits RF_ON or HV_ON low.