PCI-208 / CPCI.208 manual
31.03.2004
Page 27 of 30
Gated Sampling (option)
See the hardware description part of the manual for basic information about gated sampling.
register name
reg no.
r/w
SPC_TRIGGERMODE
40000
r/w trigger mode set to TM_GATELOW or TM_GHATEHIGH
SPC_GATEMARKENABLE
200400
r/w enables gate marking in data. value 128 (0x80) is used as mark
The gated sampling mode is enabled by settings the triggermode to TM_GATELOW or TM_GATEHIGH. The register memsize holds the
total amount of memory to be recorded. The register posttrigger has no function at gated sampling.
The sampling of data starts with the first edge of the external gate signal. At trigger mode TM_GATELOW this is the falling edge. At
trigger mode TM_GATEHIGH this is the rising edge. Data is not recorded before the first occurance of the correct edge even if the
programmed gate level is present at the input connector at start time.
The delay between the external triggerevent and the first sampled data corresponds to the used samplerate and the synchronisation and is
fix for each recording with this settings. The delay is necessary for this board because it works with dynamic RAM and needs refresh
cycles to let the data stay in memory when the board is not recording.
Samplerate
Synchronisation
Triggermode
Delay trigger to first recorded sample
d
100 MHz
No
Gate LOW or Gate HIGH
8 Samples
d
100 MHz
Yes
Gate LOW or Gate HIGH
13 Samples
200 MHz
No
Gate LOW or Gate HIGH
16 Samples
200 MHz
Yes
Gate LOW or Gate HIGH
26 Samples
Recording will pause at the end of a gate intervall (rising edge on trigger mode TM_GATELOW or falling edge on trigger mode
TM_GATEHIGH). Due to the structure of the on board memory, recording may only stop at a 16 samples (32 samples for 200 MHz mode)
alignement. So there will be 1 to 16 (1 to 32 on 200 MHz mode) additinal samples recorded after the end of the gate intervall.
When gate marking is enabled, the value 128 is filtered off from the ADC values. Valid samples values are then in the range from 127
to +127. The value 128 is used to mark the end of a gate interval / start of the nect gate interval. All additinal recorded samples after
the end of the gate interval are set to 128.
Example (trigger mode TM_GATEHIGH, no Synchronisation, samplerate
d
100 MHz):
sample
ADC data
gate signal
data witout gate marking
data with gate marking
...
...
...
...
...
-
-
1
-
-
0
y0
1
y0
y0
1
y1
1
y1
y1
2
y2
1
y2
y2
...
...
...
...
...
60
y60
1
y60
y60
61
y61
0
y61
mark = -128
62
y62
0
y62
mark = -128
63
y63
0
y63
mark = -128
-
-
0
-
-
...
...
...
...
...
-
-
0
-
-
-
-
1
-
-
1
1
1
1
1
1
1
64
y64
1 (8 samples delay)
y64
y64
65
y65
1
y65
y65
...
...
...
...
...
Gated sampling may not be used together with the option DoubleMem or the option Multiple Recording