PCI-208 / CPCI.208 manual
31.03.2004
Page 26 of 30
Samplerate register
Sets the samplerate for recording.
register name
reg no.
r/w
SPC_SAMPLERATE
20000
r/w samplerate between 1 MHz and 200 MHz
The value is a 32 bit integer in the range from 100 MHz down to 781 kHz using an 7 bit divider or the value 200 MHz. Possible values
are: 200 MHz, 100 MHz, 100 MHz/2 = 50 MHz, 100 MHz/3 = 33.33 MHz, 100 MHz/4 = 25 MHz, ..., 100 MHz/128 = 781 kHz
Double Mem (Option)
The option Double Mem allows it to use the complete on-board memory for the recording of channel 0. Normally each channel uses half of
the on-board memory and only the 200 MHz mode allows it to use the complete memory for one channel. With the option Double Mem it
is possible to use the full memory for one channel with all samplerates.
register name
reg no.
r/w
SPC_DOUBLEMEM
220100
r/w enables DoubleMem mode. 0 = disable, 1 = enable.
Using the Double Mem mode together with the Multiple Recording mode or with the 200 MHz samplerate is not allowed. When using this
option the minimum and maximum values for the memsize register are doubled.
Multiple Recording (Option)
See the hardware description part of the manual for basic information about multiple recording.
register name
reg no.
r/w
SPC_MULTI
220000
r/w enables Multiple Recording for the board. 0 = disable, 1 = enable.
SPC_MULTIMEMVALID
220200
r
read out the number of valid trigger samples after multiple recording was stopped by the user
by writing SPC_STOP to the command register.
The register memsize holds the total amount of memory to be recorded. The register posttrigger will hold the size of one segment.
Recording is started with a fixed delay after the triggerevent is found. There is no pretrigger possible in Multiple Recording mode.
If multiple recording is aborted by the user, all segments that have been recorded before the stop command may be read out. To
determine, where the recording has stopped the user may read out the number of valid samples with the help of the register
SPC_MULTIMEMVALID.
The delay between the external triggerevent and the first sampled data corresponds to the used samplerate, the synchronisation and the
uses triggermode and is fix for each recording with this settings. The delay is necessary for this board because it works with dynamic RAM
and needs refresh cycles to let the data stay in memory when the board is not recording.
Samplerate
Synchronisation
Triggermode
Delay trigger to first recorded sample
d
100 MHz
No
TTL Pos. or TTL Neg.
8 Samples
d
100 MHz
Yes
TTL Pos. or TTL Neg.
13 Samples
d
100 MHz
No
Ch0 or Ch1 Pos. or Neg.
16 Samples
d
100 MHz
Yes
Ch0 or Ch1 Pos. or Neg.
21 Samples
200 MHz
No
TTL Pos. or TTL Neg.
16 Samples
200 MHz
Yes
TTL Pos. or TTL Neg.
26 Samples
200 MHz
No
Ch0 or Ch1 Pos. or Neg.
32 Samples
200 MHz
Yes
Ch0 or Ch1 Pos. or Neg.
42 Samples