Motherboard Description
SY-P4IS2
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including the ones originating from the MCH. The Intel® 845 chipset
MCH supports interrupt re-direction for inter-processor interrupts (IPIs) as
well as upstream interrupt memory writes.
For message based interrupts, system write buffer coherency is maintained
by relying on strict ordering of Memory Writes. The Intel® 845 chipset
MCH ensures that all Memory Writes received from a given interface prior
to an interrupt message Memory Write are delivered to the system bus for
snooping in the same order that they occur on the given interface.
1-6.8 Powerdown Flow
Since the Intel® 845 chipset MCH will be powered down during STR, the
MCH can’t maintain any state information when exiting STR. This means
that the entire initialization process when exiting STR must be performed
by the BIOS via accesses to the DRC2 register.
Entry into STR (ACPI S3) is initiated by the (OS) Operating System,
based on detecting a lack of system activity. The OS unloads all system
device drivers as part of the process of entering STR. The OS then writes
to the PM1_CNT I/O register in the ICH2 to actually trigger the transition
into STR.
1-6.9 IDE support
The motherboard has two independent bus-mastering PCI IDE interfaces.
These interfaces support PIO Mode3, PIO Mode4, PIO Mode5 ATAPI
devices (e.g., CD-ROM), and Ultra DMA 33/66/100 synchronous-DMA
mode transfers. The BIOS supports logical block addressing (LBA) and
extended cylinder head sector (ECHS) translation modes. The BIOS
automatically detects the IDE device transfer rate and translation mode.
Programmed I/O operations usually require a substantial amount of
processor bandwidth freed by bus mastering IDE can be devoted to other
tasks while disk transfers are occurring.
The motherboard also supports laser servo (LS120) drivers. LS-120
technology allows the user to perform read/write operations to LS-120
(120MB) and conventional 1.44MB and 720KB diskettes. An optical
servo system is used to precisely position a dual-gap head to access the
Summary of Contents for SY-P4IS2
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