Motherboard Description
SY-P4IS2
8
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AGTL+ system bus with integrated termination supporting
32-bit system bus addressing
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Up to 3GB (w/ 512-Mb technology) of PC133 SDRAM
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1.5V AGP interface with 4x SBA/Data Transfer and 2x/4x
Fast Write capability
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8 bit, 66 MHz 4x Hub Interface to Intel ICH2
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Distributed arbitration for highly concurrent operation
1-6.2 Intel® Pentium® 4 Processor/Northwood Processor
System Bus Interface
The Intel® 845 chipset MCH is optimized for the Intel® Pentium 4
processor/Northwood processor in the 478-pin package. The primary
enhancements over the Compatible Mode P6 bus protocol are:
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Source synchronous double pumped address
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Source synchronous quad pumped data
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System bus interrupt and side-band signal delivery
In this mode, the MCH supports a 64B cache line size. Only one
processor is supported at a System bus frequency of 400 MHz. The
MCH supports a 3:4 Host-to-Memory frequency ratio (using the 100
MHz clock). The MCH integrates AGTL+ termination resistors on
all of the AGTL+ signals. The MCH supports 32-bit system bus
addresses, allowing the processor to access the entire 4GB of the
MCH memory address space.
The MCH has a 12-deep In-Order Queue to support up to twelve
outstanding pipelined address requests on the system bus. The MCH
supports two outstanding defer cycles at a time, however only one to
any particular IO interface. Processor initiated I/O cycles are
positively decoded to AGP/PCI or MCH configuration space and
subtractively decoded to the Hub Interface. Processor initiated
memory cycles are positively decoded to AGP/PCI or DRAM, and
are again subtractively decoded to the Hub Interface if under 4GB.
AGP semantic memory accesses initiated from AGP/PCI to DRAM
are not snooped on the system bus. Memory accesses initiated from
Summary of Contents for SY-P4IS2
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