71
WX-7700MDX
•
MAIN BOARD IC550 MB90574CPMT-G-382-BNDE1
(MASTER CONTROLLER (CD MECHANISM CONTROLLER) )
Pin No.
Pin Name
I/O
Description
1
SP LATCH
O
Serial data latch pulse output for spectrum analyzer display to the displayr controller
“H” active
2
DSPON
O
Power on/off control signal output for the CXD2727Q power supply “H”: power on
3
DSPLAT
O
Serial data latch pulse output to the CXD2727Q
4
DSPRST
O
System reset signal output to the CXD2727Q “L”: reset
5
ATT
O
Audio line muting on/off control signal output “H”: muting on
6
SYSRST
O
System reset signal output to the MD mechanism controller, SONY bus interface IC and display
controller “L”: reset
7
D AUDSEL
O
CD/MD selection signal output to the CD/MD selector “L”: CD, “H”: MD
Serial data 24/32 bit slot selection signal output to the CXD2727Q
“L”: 24 bit slot, “H”: 32 bit slot
8
VCC
—
Power supply terminal (+5V)
9
NCO
O
Not used
10
EE SIO
I/O
Two-way data bus with the EEPROM on the tuner unit
11
EE CKO
O
Clock signal output to the EEPROM on the tuner unit
12
RX
I
Input terminal for UART transfer data when writing into flash memory data
13
TX
O
Output terminal for UART transfer data when writing into flash memory data
14
BUSON
O
Bus on/off control signal output for SONY bus to the MD mechanism controller, SONY bus
interface IC and display controller “L”: bus on
15
BEEP
O
Beep sound drive signal output terminal “H”: beep on
16
TELMUTE
I
Telephone muting detect signal input terminal
At input of “H”, the audio signal is attenuated by 20 dB
17
UNISI
I
Serial data input from the SONY bus interface IC
18
UNISO
O
Serial data output to the SONY bus interface IC
19
UNICKO
O
Serial clock signal output for the bus interface to the MD mechanism controller, SONY bus
interface IC and display controller
20
DSPSI
I
Serial data input from the CXD2727Q
21
DSPSO
O
Serial data output to the CXD2727Q
22
DSPCKO
O
Serial data transfer clock signal output to the CXD2727Q and display controller
23
NCO
O
Not used
24
SIRCS
I
SIRCS signal input from the SIRCS controller
25
CD SI/TSI
I
Serial data input from the uPD63711GC
26
CD SO/TSO
O
Serial data output to the uPD63711GC
27
CD CKO/TCKO
O
Serial data transfer clock signal output to the uPD63711GC
28
DSPPLL
O
MD PLL clock output control signal output to the CXD2727Q
At “L” is output: PLCKL (pin
ia
) is fixed at “L”
At “H” is output: PLCKL (pin
ia
) output the PLL clock signal
29
DSPMST
O
30
NCO
O
Not used
31
VOLATT
O
Muting on/off control signal output to the TDA7402TR “L”: muting on
32
DIVER
O
Diversity selection signal output terminal Not used
Power on/off controll signal output for the CD/MD selector
“L”: power off (tuner on), “H”: power on (CD/MD on)
Bit clock (BCK) and L/R sampling clock (LRCK) signal master/slave mode selection signal
output to the CXD2727Q “L”: master mode, “H”: slave mode
