Sony WRT-822B, Service Manual

Page: 37 / 46

6-1
WRT-822B
Section 6
Block Diagram
Description
WRT-822B is comprised of the following:
MB-940 board
Audio and peripheral circuit block; Ref. No. 100s and 200s
PLL and RF circuit block; Ref. No. 300s
CPU and peripheral circuit block; Ref. No. 400s
Power supply circuit block; Ref. No. 500s
Audio and peripheral circuit block
The audio signal which is input from the AUDIO input con-
nector (CN100) is input into the transformer (T100) as an
balance signal.
The audio signal which is outputted from the transformer
(T100) is input into the Audio attenuator (ATT) circuit
(IC100).
The ATT can be set between 0 to 21 dB in 3 dB steps by
switching the resistance value using analog switch (IC100).
The control signal for the analog switch is the 3 bits (ATT0,
ATT1, ATT2) signal that has been sent from the CPU
(IC402).
This signal is set by the information on
+
or
_
switches
(S400 and S401) input to the CPU.
The audio signal which is adjusted the volume by the ATT
circuit is amplified by IC101(1/2), then input into the com-
pressor circuit (IC104) via the low-pass filter (F102) and
buffer amplifier (IC203-1/2).
The audio signal is compressed to a signal level of 2:1 (1/2)
by the compressor circuit and then inputs into the pre-em-
phasis circuit. Note that time constant for the pre-emphasis
is 50
u
s.
The audio signal is mixed with the tone signal (X201,
32.768 kHz) and battery alarm signal (X200, 32.782 kHz)
and is sent RF circuit block (VCO,CP300) via the AF switch
(IC202) and AF filter (IC230).
The A/D converter circuit (IC102, D104, D400) detects the
audio signal and converts into DC level voltage. The con-
verted signal (ALO signal) is sent to the CPU and is used to
indicate the input audio signal level on the LCD (ND400).
PLL and RF circuit block
The oscillation circuit utilizes the PLL frequency synthesiz-
er method. The VCO (CP300) acts as an oscillator and mod-
ulator for the carrier frequency through voltage control.
The carrier frequency is controlled by the serial data (PLL
data) sent from the CPU to the PLL IC (IC300).
The signal is amplified by the RF amplifier circuit
(Q303,304) is output from the antenna via the low-pass fil-
ters and isolator (CP301).
Further the voltage comparator (Q300) detects the lock con-
dition of the PLL by inputting the output signal (LD signal)
from the phase comparator in the PLL IC, and sends the sig-
nal to CPU.
The voltage control circuit (Q301, 302) performs ON/OFF
control of the power voltage for the RF circuit. This control
signal is the RFM signal from the CPU. (When the RFM
signal switches “L”, the power is provided to the RF circuit.)
CPU and the peripheral circuit block
The CPU (IC402) is a 4-bit microprocessor, and the clock is
used a 4 MHz (X400, IC400).
The CPU sends out the PLL data, and controls the AF mute,
RF mute, ATT, LCD, and so on.
The PLL (frequency) data have been written to the EE-
PROM (IC405).
The voltage detector circuit (IC403, 404) detects the power
supply voltage (
+
2.0 V) and uses it to reset the CPU.
Also, the reference voltage circuit (R402, C401) generates a
3.0 V which is used by the CPU as the reference for detect-
ing battery voltage and AF indicator voltages.
Power supply circuit block
The DC-DC converter circuit (IC500, Q500, Q501, Q502,
D500, D505) extracts the 5 V (Vcc1) from the 3.0 V battery
voltage and supplies to audio section.
The DC-DC converter circuit (IC501) extracts the 3.3 V
(Vcc2) from the 5 V (Vcc1) and supplies to RF and CPU
sections.
The power switch circuit performs ON/OFF control of volt-
age input to the DC-DC converter. This is controlled by
power switch circuit (S500, Q503, Q510) and CPU (IC402).