Sony WRT-807B, Service Manual

Page: 51 / 64

6-1
WRT-807B (U/CE)
Section 6
Block Diagram
Description
WRT-807B is comprised of the following :
MB-860 board
Power supply circuit block ; Ref. No. 100s
Audio circuit block, PLL and RF circuit block;
Ref. No.300s and 400s
DP-306 board
CPU and peripheral circuit block, display and operation
block; Ref. No. 200s
CN-1868 board
Audio input connector; Ref. No. 300s
Audio and peripheral circuit block
The audio signal which is input from the DM unit is input
into MB-860 board via CN-1868 board.
The audio signal is input into the Audio attenuator (ATT)
circuit via the EMI filter.
The ATT can be set between 0 to 21 dB in 3 dB steps by
switching the resistance value using analog switch (IC305).
The control signal for the analog switch is the 3 bits (ATT0,
ATT1, ATT2) signal that has been sent from the CPU
(IC200).
This signal is set by the information on
+
or
_
switches
(S200 and S201) input to the CPU.
The audio signal which is adjusted the volume by the ATT
circuit is amplified by IC306, then input into the compressor
circuit (IC309).
The audio signal is compressed to a signal level of 2:1 (1/2)
by the compressor circuit and then inputs into the pre-em-
phasis circuit. Note that time constant for the pre-emphasis
is 50
u
s.
The audio signal which is limited the amplitude by the clip-
ping circuit (IC307-2/2) is mixed with the tone signal
(X301, 32.768 kHz) and battery indicator tone signal (X302,
32.782 kHz), and is sent RF circuit block (VCO, CP301).
The A/D converter circuit (IC308, D302) detects the audio
signal and converts into DC level voltage. The converted
signal (ALO signal) is sent to the CPU and is used to indi-
cate the input audio signal level on the LCD (ND200).
RF circuit block
The oscillation circuit utilizes the PLL frequency
synthesizer method. The VCO (CP301) acts as an
oscillator and modulator for the carrier frequency through
voltage control.
The carrier frequency is controlled by the serial data (PLL
data) sent from the CPU to the PLL IC (IC304).
The signal amplified by the RF amplifier circuit (Q314,
315) is output from the antenna via the isolator (CP300).
Further the voltage comparator (Q310) detects the lock
condition of the PLL by inputting the output signal (LD
signal) from the phase comparator in the PLL IC, and
sends the signal to CPU.
The voltage control circuit (Q312, 313) performs ON/
OFF control of the power voltage (
+
3.0 V) for the RF
circuit. This control signal is the RFM signal from the
CPU. (When the RFM signal switches “L”, the power is
provided to the RF circuit.)
CPU and the peripheral circuit block
The CPU (IC200) is a 4-bit microprocessor, and the clock
is used a 4 MHz (X200, IC203).
The CPU sends out the PLL data, and controls the AF
mute, RF mute, ATT, LCD display, and so on.
The voltage detector circuit (IC201) is used to reset the
CPU.
The EEPROM (IC201) is used to store the setting data.
Also, the reference voltage circuit (R209, C207) generates
a 3.0 V which is used by the CPU as the reference for
detecting battery voltage and AF indicator voltages.
Power supply circuit block
The DC-DC converter circuit (IC101, Q101, Q102, Q103,
T101, L101) extracts the 5 V from the 1.5 V battery
voltage and supplies to audio section.
The DC-DC converter circuit (IC102, Q107, Q108, Q109,
T102, L102) extracts the 3 V from the 1.5 V battery
voltage and supplies to RF and CPU sections.
The power switch circuit performs ON/OFF control of
voltage input to the DC-DC converter.
POWER ON is performed by the power switch circuit
(S101, Q105, Q106).
POWER OFF is performed by the power hold circuit
(Q104, Q110) that is controlled by the CPU. The CPU
controls the power hold circuit by detecting the power
switch condition. The control signal is POWER-HOLD
signal.