Sony TVP-08, Training Manual

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35
Reset
Overview
There are two reset circuits in the RA-4 chassis. The first reset occurs at
initial plug-in, and the second each time the set is powered ON. The initial
plug-in reset only resets IC1008 Main CPU. All other ICs that need reset-
ting are reset each time the set is turned ON.
Initial Reset
When the set is plugged-in, S5 volts is developed on the G board.
This voltage is sent to the A board from CN6101 to CN505. This voltage
is called RM+5 on the G board and ST-5V on the A board. It is then
applied to IC1008 Main CPU and IC1010 Reset. The purpose of IC1010
Reset is to hold the reset line low until the voltage on the ST-5V line
reaches a threshold around 4.3 volts. When this threshold is reached,
IC1010/4 is released from ground and current flows through pull-up resis-
tor R1117 and R1126. In reset, IC1008/9 I Reset is held low until C1033
charges. C1034 and C1036 are used to filter out any noise or spikes that
may occur on the reset line. IC1008 Main CPU will begin to function after
reset occurs.
After IC1008 Main CPU is reset, the data is read from IC1007 NVM and
stored in its own internal RAM. This data contains information on such
things as global video settings, video mode presets and user settings,
etc. It does not contain the data for Registration or MID settings. After
this data is read, the data and clock lines will be high with periodic low
going pulses. The CPU is now awaiting further instructions. This B I²C
bus is the only active bus when the unit is in standby mode. While the set
is running, it will have the same data present as the Main or M I²C bus.
If the reset line is held LOW for some reason, the set would appear to be
completely dead. X1001 and X1002 would continue to oscillate. IC1008/
38 and 39 are only active when Closed Caption is selected. These pins
are for CCD OSD horizontal positioning and will have a 12 MHz signal on
them when closed captioning is ON. IC1008/48 B Data and IC1008/50 B
Clk would be HIGH with no activity on them. You would normally always
see some activity on these lines.
Power ON Reset
When the set is powered ON, there is a LOW going reset pulse sent from
IC1008/45 O RSTCTL to IC1009/60 I Reset that resets IC1009 OSD CPU.
This reset pulse is also sent to Q1015 Inverter. Q1015 inverts this pulse
to a HIGH going reset pulse. It is then distributed to other parts of the set
that need resetting. This reset pulse is sent to CN518/18, which is con-
nected to the BM board, and CN522/10, which is connected to the BD
board
. It also goes to Q1359 Inverter where it is inverted and then sent to
IC1306/57 RST B. IC1306 is the 3D Comb Filter. Once this reset has
occurred and the set is operating, timing for the I²C bus is set by the VP
pulse, which is input to IC1008/25 and IC1009, as well as the other CPU’s
in the set. This pulse allows synchronization of the data. Once it is re-
ceived, there will always be activity present on the M and B I²C busses.
One “bug” that may be encountered, although very rarely, has to do with
reset and S-Link. You may experience a problem since IC1009 OSD
CPU is not reset at initial plug-in and the S-Link signal is input to IC1009
OSD CPU. If an S-Link power up signal is sent to the set after it was
unplugged and then plugged back in, but before it was turned ON, the set
may not respond to the S-Link signal. However if the set was unplugged,
re-plugged and turned on at least once, this will not occur.