Sony TVP-08, Training Manual

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87
H BLK Delay and ½ H + Odd/Even
Overview
The VDSP IC requires a 15.734 KHz square wave input for its countdown
circuit. The HS signal goes through the H BLK Delay circuit, which stretches
the HS pulse so that it becomes a square wave. This signal is then ap-
plied to the ½ H and Odd/Even circuit along with the VS signal. This
circuit produces two outputs. The first is the ½ H signal that is a 15.734
KHz square wave. The second output is the Odd/Even pulse. This signal
is a 30Hz square wave, which is used by the OSD Processor and the BD
board.
H BLK Delay
The VDSP requires a horizontal frequency square wave to operate its
countdown circuit. Since the HS pulse is not a square wave, we need to
stretch it so that a pulse is created that starts at the same rising edge but
has a 50/50-duty cycle. This is done using IC517 H BLK Delay, which
uses two identical delay circuits to lengthen the width of the HS pulse.
IC217 H BLK Delay contains two identical circuits which contain a two
input OR gate with one input bubbled, and a pulse delay circuit with Q and
NOT Q outputs.
The HS signal is input to IC517/12 HS. IC517/11 B2 is tied to the Def 5
volts. Since an OR gate produces a HIGH output any time one of its
inputs is HIGH, the gate inside IC517 will be HIGH whenever the HS
pulse is HIGH. This pulse is input into the delay circuit. The output’s
HIGH to LOW transition is delayed by the time constant of R661 and
C576, which are to IC517/14 C2/R2. The delayed signal is output at
IC517/10 Q2.
IC517/10 Q2 is then sent through R663 to IC517/5 HS1. Since this is a
bubbled input to the OR gate and IC517/4 A1, the other input, is con-
nected to ground, the output is of the OR gate will be HIGH whenever the
input of pin 5 is LOW. This signal is delayed by the time constant of R670
and C580, which are connected to IC517/2 C1/R1. This delayed signal is
output at IC517/6 Q1.
½ H and Odd/Even
The output from IC517/6 is input to two pins on IC508 ½ H and Odd/Even.
They are IC508/3 1Clk and IC508/12 2D. Each of these inputs is for one
of the two D flip-flops inside IC508.
In flip-flop 1, the signal from IC517/6 is input to the clock input. The data
input at IC508/2 is tied to IC508/6 NOT Q. When the data input of a D flip-
flop is tied to its NOT Q output, the circuit will output a signal that is the
Clk signal divided by 2. This means that the output at IC508/5 1Q will be
half the input frequency of the input at IC508/3 1Clk. This signal is called
½ H and is output to IC512/16.
In flip-flop 2, the signal from IC517/6 is input into the data input. The
clock input has the VITM signal input to it. The VITM pulse from IC512/22
is also called VBLK and is a short pulse timed at the vertical blanking
interval. Each of these pulses represent a field of video. The flip-flops
output can only change state when the clock pulse is on its positive edge
and the two inputs are timed so that the data input is HIGH or LOW for
every other clock pulse. The result is a HIGH signal being output from Q
on the first clock pulse and a LOW being output on the second clock
pulse. Since the output of this circuit is taken at IC508/8 NOT 2Q instead
of 2Q, our result would be opposite. The end result is a 30 HZ square
wave output at IC508/8. The LOW periods of this signal represent the
odd fields and the HIGH outputs represent the even fields. The BD board
and IC1009 OSD CPU use this signal.
IC517/12
2V20us IC517/6
2V 20us
IC508/5
2V 20us
IC508/11
2V 10ms