Sony RM-PJM50, Manual

Page: 74 / 178

4-14
VPL-FX50
4-6-2-2. Explanation of the Block Diagram
RGB each color 8 bits digital data from scan converter
(DR0 thru 7, DG0 thru 7, DB0) are digitally processed to
3D
γ
and W/B by the
γ
block.
In the D/A block, the output
γ
signal is converted to
analog RGB signals from digital signals. Then, the RGB
Amp. Block in the later stage adjusts the RGB signals to
an appropriate input level for the panel driver block.
After doing those reverse, amplification and sample
holding process in the driver block, those signals are sent
to the LCD panel.
Since the
γ
block incorporates a timing generator, gener-
ates sorts of timing signals from DCLK (Dot clock) of
scan converter output signals, DVS(V-SYNC), and
DHS(H-SYNC). These timing signals are required to
drive panel driver block and LCD panel.
“Control D/A Block “ converts the data from IICBUS to
voltage and outputs such level of VCOM, etc.
4-6-2-3. Explanation of the Main Block
(1)
γ
Block
The block is formed by 3D
γ
processes, IC5701 which
generates timing signal for LCD panel control and its
peripherals.
.
IC5701 moves against the waveform width and the
DC level against the input digital video signals. It
corresponds with contrast and bright control
performed by a user.
.
W/B processing: Adjust hue by moving the width
and DC level( Gain and Bias ) of each RGB wave-
form individually.
.
Composition of internal pattern and OSD
.
γ
& 3D
γ
correction
IC5701 generates the following timing signals with DVS,
DHS and DCLK.
HST: Starting pulse to drive H SHIFT register of LCD
panel
HCK1 (R, G, B):
Clock to drive H SHIFT register of LCD panel
HCK2 (R, G, B):
Reversal clock of HCK1
VCK: Clock to drive V SHIFT register of LCD panel
VST: Starting pulse to drive V SHIFT register of LCD
panel
PCG: Pulse to improve uniformity of the LCD panel
ENB: Enable pulse input to select the gate of LCD panel
RGT: Switching signal of the scan direction
PRGPLS:
Pulse to define the width of the 1st stage of PSIG
(to improve the uniformity of LCD panel)
FRP: Pulse to reverse the video signals to PSIG
DWN:
Signal to reverse the video image upside down
SID: 3value signal to generate PSIG
ENBP:
Gate selecting pulse of LCD panel
POS-CON (1, 2):
Adjusting signal for the sample-hold timing
CLP: Clamp timing signal of video signals
(2) D/A Block
The D/A block is structured by 10 bits 3ch D/A
converter (IC5704) and by its peripherals.
It converts digital signals (R, G, B) from
γ
block to
analog signals (R, G, B).
(3) RGB Amp. Block
This block is built with RGB AMP (IC5301) and its
relative circuits.
It firstly executes DC cut of the analog signals (R, G,
B) in the D/A block, clamps them using the CLP
signal that was generated in the 3D@g@ block,
adjusts both waveform width and the DC level the
input level of next stage panel driver, and then outputs
through the emitter follower.
(4) R (G, B) Panel Driver Block
Panel Driver Block consists of IC5306 (CXA3512R)
and IC5308 (CXA3512R).
This IC CXA3512R has line reversible AMP., afford
to amplify gain by 3 times. The AMP output is
performed sample-hold b by every 6 dots on the LCD
panel, timing aligned, and then output to the LCD
panel.
As the LCD adopted in this Set performs based on 12
dots one time sample, uses circuit of 2 pieces of
CXA3512R alternately connected per every dot of
sample-hold function.
In addition, this block has functions to line reverse SID
value signal, generated in the 3D@g@, to amplify and
to drive PSIG to the LCD panel through a transistor.