RCD-W3
35
35
5-9.SCHEMATIC DIAGRAM
–
BD-R SECTION (6/6)
–
• See page 46 for IC Pin Function Description.
R401
R402
R403
R404
R405
R400
C401
D402
R412
R414
C402
C403
C404
C494
C495
R496
R497
R498
R499
C491
R493
R494
R495
L491
R424
C410
C411
C412
X402
R425
R416
R417
R418
R419
R420
R421
C497
C496
C498
C499
R413
R410
R422
R423
R427
R426
PN403
C493
C492
R407
R492
X401
R411
DZ401
Q402
100
100
100
100
100
4.7k
0.1
KDS187
100k
100
0.1
1
0.1
100
16V
0.1
27k
4.7k
22k
10k
330p
100k
10k
10k
4.7k
0.1
15p
15p
20MHz
4.7k
100
100
0
0
0
0
8200p
0.1
0.01
0.01
0
100
4.7k
4.7k
0
100
22P
220
6.3V
0.1
100
0
33.86MHz
10k
DAN202K
KTD1304S
SWITCH
5VU
5VM
CDP 33M
B4-6
B5-6
FAO
TAO
MDP
SW
SAO
VFC
FE
TE
VCC 3.3V
PWR FAIL
F/T
SLD ERR
5VA
GND
8V
B3-6
F+
T+
T-
F-
GFS
SQSO
FOK
CXD XLAT
CXD MD2
CXD XTSL
RESET
CXD DATA
SENS
CXD CLOK
FL SCK
FL CE
FPGA RST
PWR MUTE
L-
L+
OPCL SW1
OPCL SW2
A
/A
/B
B
HV+
HW-
HW+
HU-
HU+
H+
H-
HV-
V
W
U
PWR CTL
FW EN
FL SDI
PROG DN
FPGA CS
FPGA CLK
FPGA WD
FPGA AS
DAC CS
REC RXD
REC TXD
AS PROG
EXT RMC
XTU
FPGA RST
MD2
TRK INC
LEVEL IN
L-
L+
OPCL SW1
OPCL SW2
A
/A
/B
B
HV+
HW-
HW+
HU-
HU+
H+
H-
HV-
V
W
U
LEVEL SEL
DUB SEL
KEY IN2
KEY IN0
KEY IN1
SCOR
COUT
SCLK
SQCK
REMO IN
SL1IN
SL2IN
ASL2
SL2+
SL2-
GND
RSL1
SL1+
SL1-
GND
W
V
U
RSP
HV-
HU+
HU-
HW+
HW-
HV+
OSC
MU1
LDIN+
BRS
LO-
LO+
FO-
FO+
GND
TO+
TO-
5VCC
GND
TOIN
FOIN
SPIN
REF
FG
HB
VM1(8V)
VM2(8V)
VM3(5V)
MOTOR DRIVER
M63021FP
XTAL
EXTAL
/STBY
/RESET
VREF(4V)
SYSTEM
CONTROL
VCL
MD2
MD1
MD0
Y1
Y0
Z1
INHIB
VEE
VSS
Z0
Z
VCC
Y
X
X1
X0
CTLZ
CTLY
CTLX
DATA SELECT
IC407
1
5
10
15
20
22
U
W
V
GND
HV-
H-
HU+
HU-
HW+
HW-
HV+
H+
SLEDIN SW
GND
B
A
L+
L-
OPCL SW1
OPCL SW2
/A
/B
C4A2
C4A0
C4A1
2.2
2.2
2.2
2.2
15k
15k
R4C8
R4C9
R4CA
R4CC
C4A8
C4A9
2.2
2.2
2.2
2.2
R4C4
R4C5
R4C6
R4C7
16V
100
C4A6
C4A7
0.1
R4C0
R4A9
R4A8
R4C3
R4A1 10k
0
0
0
0
R4S8
R4S6
R4S4
R4S2
JIG DOWN
OPTION 4
SENS
GFS
SQSO
FOK
GND
CXD CLOK
CXD XLAT
CXD DATA
CXD MD2
CXD XTSL
DUB SEL
RESET
5V
DAC CS
TRK INC
SW REF/AUD
FPGA AS
DRV MUTE
FW EN
SW
CXA VFC
TRAYCTRL
GND
AS DATA
REC TXD
FL SDI
PROG DN
AS CLK
FL SCK
FL CE
FPGA RST
GND
FPGA DATA
FPGA CLK
FPGA CS
R4F0
R4F1
100
100
C4E6
1000p
R4F2
R4F3
10k
10k
RESET
IC409
C4F6
220
6.3V
R4F7
10k
R4F9
27k
R4F8
82k
C4F7
1
C4F8
1
XIN
XOUT
S1
LF
VCC
S0
FSOUT
VSS
R4K7
0
R4E7
33
R4E5
0
R4G3
0
R4K6
0
C4E3
0.01
C4E1
10p
C4E2
10p
R4E3
3.3k
C4E5
0.1
IC408
5V
GND
PWR MUTE
PWR CTL
GND
OPTION 1
OPTION 2
OPTION 3
T1RYSW
TRYSW2
5VA
KEY IN1
KEY IN0
KEY IN2
TE/FE
1.35/AUD
SLD CTL B
SLD ERR
SLD CTL A
AGND
SPD G UP
SCOR
SLDIN SW
GND
COUT
SQCK
FG
SCLK
AS PROG
AS FCS/TRK
REMO IN
R4A0
18k
R4A3
10k
R4C2
220
PWR FAIL IN
R4C1 220
R4A2 470
IC405
10k
10k
R4A5
R4A4
R4A6
R4A7
470
470
IC406
GND
IN
OUT
AUD LR
SW
R4L9 0
R4M2 22k
C4G3 1000p
C4G2 1000p
C4G1 1000p
R4G2 18k
R4G1 18k
R4G0 18k
10k
10k
4700p
4700p
470p
C4A3
470p
C4A5
470p
C4A4
CLOCK OSC
FS781BZB
XC61CN3002
HD64F3062BFBL-W3CDP
BU4053BCFV-E2
0.1
0.1
0.1