RCD-W3
25
25
– CDP SECTION –
34
3
6
7
8
9
10
11
27
RF SUM
AMP
35
32
31
9
10
24
26
36
37
28
27
12
13
14
21
20
19
18
17
16
23
M
M
M
A
RF
B
C
D
E
F
A
B
C
D
E
F
V.C
VCC
LD
F+
F-
T+
T-
A
A
B
B
L+
L-
MD
VR
LD
PD
FO+
PD
LD
2
3
1
FCS+
FCS-
TRK+
TRK-
FO-
TO+
TO-
SL1+
SL1-
LO+
LO-
W
W
V
U
HU+
HU-
HV+
HV-
HW+
HW-
H-
H+
SLEDIN SW
+5VA
LIMIT
SW
V
U
HU+
HV+
HW+
HU-
HV-
HW-
HB
FOIN
TOIN
MUTE
SL1IN
MU1
LOIN+
REF
SPIN
FG3
DRV
DRV
95
2
3
4
41
1
40
DRIVE
CONTROL
HALL
SENSOR
FOCUS
COIL
TRACKING
COIL
M902
SLED
MOTOR
(DECK A)
5
6
SL2+
SL2-
SL2IN
DRV
2
M903
LOADING
MOTOR
(DECK A)
M901
SPINDUL
MOTOR
(DECK A)
BTL MOTOR DRIVE
IC405
DRV
DRV
OPTICAL
PICK-UP BLOCK
(DECK A)
23
24
2
25
8
75
10
15
38
14
13
59
17
18
100
78
79
80
12
6
60
26
67
66
93
99
18
1
2
10
45
41 42 43 96 48
40 47 39
89 46 94
20
89
92
85 86 87 83 82
69 57 66
73 78 79
80
84
95
85
5
3
82
9
90
83
7
87
4
70
48
49
47
71
EFM
DEMODULATOR
D/A
PROCESSOR
DIGITAL
OUT
SERIAL/
PARALEL
PROCESSOR
REGISTER
AC
AMP
VC
VC
DVC
EQ_IN
A
B
C
D
E
F
EQ
FOCUS
ERROR
AMP
TRACKING
ERROR
AMP
APC
LD
DRIVER
Q501
ANALOG
SWITCH
•
AMP
•
A/D
CONVERTER
SERVO
DSP
CPU
INTERFACE
28
15
16
18
20
29
17
21
ERROR
CORRECTOR
32K
RAM
CLOCK
MUTE
67
12
13
DATA BUS
CDP 33M
FPGA RST
MD2
FWEN
PROG DN
FL SDI
+5VU
TRK INC
PWR MUTE
LEVEL SEL
LEVEL IN
REC RXD
REC TXD
DUB SEL
CHECK
CONNECTOR
P BCK
P DATA
P DOUT
P LRCK
CXD MUTE
DOUT
PCMD48
BCK48
LRCK48
MUTE
XTLO
XTLI
MCKO
NC
NC
SW
PWR MUTE
/RESET
EXTAL
XTAL
TRK INC
AS DATA
REC TXD
DUB SEL
PROG ON
FW EN
MD2
FPGA AS
DAC CS
FPGA CS
FPGA CLK
FPGA DATA
FPGA AS
DAC CS
FPGA CS
FPGA CLK
FPGA WD
IC409
FG
AS FCS/TRK
SYSTEM
CONTROL
IC407
CLOCK
OSC
IC408
DATA SELECTOR
IC406(1/2)
SELECT DATA
IC406(2/2)
SW
SLDCTL A
SLDCTL B
TRAYCTRL
SLD ERR
DRV MUTE
CXA VFC
SLEDIN SW
1.35/AUD
SW REF/AUD
SPD G UP
SPNFG
SW
SLDCTL A
SLDCTL B
TRAYCTL
SLD ERR
DRV MUTE
VFC
SLDIN
T1 RYSW
TRYSW2
PWR CTL
FL SDI
FL SCK
REMO IN
KEY IN0
FL CE
KEY IN1
KEY IN2
POW CTL
FLD TXD
FLD CLK
RMC IN
KEY_IN0
FLD CS
KEY_IN1
KEY_IN2
52
51
SW4M1
(LOADING/OPEN)
(DECK A)
+2.7V
+5VA
(LOADING)
TRAY
OPEN
( )
RF AMP
IC403
FEI
RFDCO
RFAC
RFDCI
FE
TE
CE
CEI
12
25
24
25
27
26
36
23
28
FAO
TAO
DRV_MUTE
SLDCTLA
SLDCTLB
TRAY CTL
SAO
SPNFG
MDP
SLD IN
VFC
VFC
SW
SW
SLD ERR
Q402
SE
TE
CE
FAO
TAO
MDP
SAO
VC
FAO
TAO
MDP
SAO
FE
RFDC
RFAC
+2.7V
REG
IC410
COUT
FOK
DATA
XLAT
CLOCK
SCLK
SENS
MD2
GFS
XTSL
SQSO
SCOR
SQCK
XRST
DIGITAL SERVO
DIGITAL SIGNAL PROCESSOR
IC402
+5VA
ERROR AMP
IC404
2
1
COUT
TE/FE
FOK
CXD DATA
CXD XLAT
CXD CLK
SCLK
SENS
CXD MD2
GFS
CXD XTSL
SCOR
SQSO
SQCK
FPGA RST
D
CD-R
SECTION(2/2)
(Page 24)
E
AUDIO
SECTION
(Page 26)
F
POWER
SECTION
(Page 27)
15
12
13
11
14
25
14
63
1
2
RESET
X402
20MHz
X401
33.86MHz
PN402
1
2
6
DRIVE
FS OUT
XTAL
OSC
XIN
XOUT
•Signal Path
: CD PLAY
: CD (DIGITAL)