Sony MHC-V77DW, Service Manual

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MHC-V77DW
98
BENTEN-MOTHERBOARD BOARD (4/11) IC6341, IC6342 NT5CB128M16IP-EK (SD-RAM)
Pin No. Pin Name I/O Description
A1 VDDQ_A1 - DQ Power Supply: 1.5V +/-0.075V
A2 DQU5 I/O Data Input/output: Bi-directional data bus.
A3 DQU7 I/O Data Input/output: Bi-directional data bus.
A4 NO_USE - Not used
A5 NO_USE - Not used
A6 NO_USE - Not used
A7 DQU4
I/O
Data Input/output: Bi-directional data bus.
A8 VDDQ_A8
-
DQ Power Supply: 1.5V +/-0.075V
A9 VSS_A9 - Ground
B1 VSSQ_B1 - DQ Ground
B2 VDD_B2
-
Power Supply: 1.5V +/-0.075
B3 VSS_B3
-
Ground
B4 NO_USE
-
Not used
B5 NO_USE
-
Not used
B6 NO_USE
-
Not used
B7 DQSU
I/O
Data Strobe: Output with read data, input with write data. Edge-aligned with read data, cen-
tered in write data. For the x16, DQSL: corresponds to the data on DQL0-DQL7; DQSU corre-
sponds to the data on DQU0-DQU7. The data strobe DQS, DQSL and DQSU are paired with
differential signals DQS, DQSL and DQSU, respectively, to provide differential pair signaling
to the system during reads and writes. DDR3 SDRAM supports differential data strobe only
and does not support single-ended.
B8 DQU6
I/O
Data Input/output: Bi-directional data bus.
B9 VSSQ_B9
-
DQ Ground
C1 VDDQ_C1 - DQ Power Supply: 1.5V +/-0.075V
C2 DQU3 I/O Data Input/output: Bi-directional data bus.
C3 DQU1
I/O
Data Input/output: Bi-directional data bus.
C4 NO_USE
-
Not used
C5 NO_USE
-
Not used
C6 NO_USE
-
Not used
C7 DQSU I/O
Data Strobe: Output with read data, input with write data. Edge-aligned with read data, cen-
tered in write data. For the x16, DQSL: corresponds to the data on DQL0-DQL7; DQSU corre-
sponds to the data on DQU0-DQU7. The data strobe DQS, DQSL and DQSU are paired with
differential signals DQS, DQSL and DQSU, respectively, to provide differential pair signaling
to the system during reads and writes. DDR3 SDRAM supports differential data strobe only
and does not support single-ended.
C8 DQU2 I/O Data Input/output: Bi-directional data bus.
C9 VDDQ_C9
-
DQ Power Supply: 1.5V +/-0.075V
D1 VSSQ_D1
-
DQ Ground
D2 VDDQ_D2
-
DQ Power Supply: 1.5V +/-0.075V
D3 DMU
I
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM
is sampled HIGH coincident with that input data during a Write access. DM is sampled on
both edges of DQS. For x8 device, the function of DM or TDQS/ TDQS is enabled by Mode
Register A11 setting in MR1.
D4 NO_USE
-
Not used
D5 NO_USE
-
Not used
D6 NO_USE
-
Not used
D7 DQU0 I/O Data Input/output: Bi-directional data bus.
D8 VSSQ_D8 - DQ Ground
D9 VDD_D9 - Power Supply: 1.5V +/-0.075
E1 VSS_E1 - Ground
E2 VSSQ_E2 - DQ Ground
E3 DQL0 I/O Data Input/output: Bi-directional data bus.
E4 NO_USE - Not used
E5 NO_USE - Not used
E6 NO_USE
-
Not used