Sony MHC-V77DW, Service Manual

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MHC-V77DW
95
BENTEN-MOTHERBOARD BOARD (1/11) IC6002 MT6323L (POWER MANAGEMENT)
Pin No. Pin Name I/O Description
A1 SYSRSTB I Watchdog reset from AP
A2 SRCLKEN I Enables 26MHz CLK
A3 XIN I
1. One of 32K crystal connection port while using crystal to generate 32kHz clock
2. Tie to ground with 32kHz crystal absence
A4 XOUT I
1. One of 32K crystal connection port while using crystal to generate 32kHz clock
2. External 32kHz clocks input with 32kHz crystal absence
A5 DVDD18_IO - Power of VIO18 IO/CORE
A6 AUD_MISO O Uplink AUDIO ADC serial data
A8 DVDD18_DIG - Power of VDlG18
A10 FSOURCE - EFUSE power source
A11 CHG_DM I USB D- for BC1.1 standard
A12 CHG_DP I USB D+ for BC1.1 standard
A13 VCDT I Fractional charger input voltage for charger detection
A14 VBAT_VPA_A14 - Battery power supply input of VPA
A15 VPA_A15 O SW node of VPA
B1 AUXADC_AUXIN_GPS I AUXADC input
B2 AVSS28_AUXADC - GND for AUXADC
B3 GND_LDO_B3 - Ground for LDO
B6 SIM2_AP_SCLK I AP/PMIC SIM2 clock
B7 SPI_CSN I SPI interface's chip select signal to identify which device is selected
B8 AUD_MOSI I Downlink DAC serial data
B9 SPI_MISO I/O SPI interface's serial data signal.Default: Output only.
B10 SPI_CLK I SPI interface's clock
B11 ISINK3 O Current sink channel 3 output
B13 VPA_FB I Feedback of VPA
B14 VBAT_VPA_B14 - Battery power supply input of VPA
B15 VPA_B15 O SW node of VPA
C1 AVDD33_RTC - RTC LDO output. Supply of RTC macro where backup battery can be added.
C2 AUXADC_VREF18 O 1.8V AUXADC reference output
C5 RTC_32K2V8 O RTC domain 32kHz clock output
C7 INT O
Default: Output 0
Interrupt to BB, high active
C8 SIM1_AP_SCLK I AP/PMIC SIM1 clock
C9 AUD_CLK I 26M clock (can be hopping)
C10 ISINK0 O Current sink channel 0 output
C11 ISINK1 O Current sink channel 1 output
C13 VPROC_FB I Feedback of VPROC
C15 VPROC_C15 O SW node of VPROC
D2 AVDD28_AUXADC - 2.8V power input for AUXADC
D3 AU_VIN0_P I Analog input 1 positive
D4 AU_VIN0_N I Analog input 1 negative
D5 GND_LDO_D5 - Ground for LDO
D6 RTC_32K1V8 O VIO18 domain 32kHz clock output
D7 SIM2_AP_SRST I AP/PMIC SIM2 SRST
D8 SIM1_AP_SRST I AP/PMIC SIM1 SRST
D9 SPI_MOSI I/O
SPI interface's serial data signal.
Default: lnput only.
D11 ISINK2 O Current sink channel 2 output
D13 GND_VPROC_FB I Remote sense on ground of VPROC
D15 VPROC_D15 O SW node of VPROC
E1 AU_VIN2_N I Analog input 3 negative
E2 AU_VIN2_P I Analog input 3 positive
E6 GND_LDO_E6 - Ground for LDO
E9 GND_LDO_E9 - Ground for LDO
E11 GND_ISINK - GND for ISINK
E13 GND_VPROC_E13 - Ground of VPROC