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MDS-JE480
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• IC201 CXD2664R Digital Signal Processor, Digital Servo Signal Processor (BD BOARD)
Desription
Pin No.
Pin Name
I/O
Not used (open)
Track jump detection signal output to the system control
In the state of executire command signal output
Not used (open)
Power supply
Serial data input from the system control
Serial clock signal input from the system control
Serial latch signal input from the system control
Ground
Serial reading data output to the system control
Internal status (SENSE) output to the system control
Reset signal input from the system control
“L”: Reset
Subcode Q sync (SCOR) output to the system control
Digital In U-bit CD format or MD format subcode Q sync (SCOR) output to the system
control
Laser power switching input from the system control
“H”: Recording, “L”: Playback
Interrupt status output to the system control
Recording data output enable input from the system control
Power supply
System clock input (Fixed at “L”)
System clock input (Input terminal during OSCN:“H” )
Internal oscillating circuit control signal input
Ground
System clock frequency setting
Digital audio input (Optical input)
Digital audio input (Optical input) (Not used)
Digital audio output (Optical output) (Not used)
Serial data input
LR clock input
Serial data bit clock input
Power supply
Ground
Data input from the A/D converter
Data output to the D/A converter
LR clock output for the A/D and D/A converter
Bit clock output to the A/D and D/A converter
256Fs clock output (Not used)
Write enable signal output for DRAM
Read enable output for DRAM
Power supply
Ground
DRAM address output (Not used) (Open)
Data input/output for DRAM
* O (3) for 3-state output in the column I/O
MNT0 (FOK)
MNT1 (SHCK)
MNT2 (XBUSY)
MNT3 (SLOC)
VDC0
SWDT
SCLK
XLAT
VSC0
SRDT
SENS
XRST
SQSY
DQSY
RPWR
XINT
TX
VDIO0
OSCI
OSCO
OSCN
VSIO0
XTSL
DIN0
DIN1
DOUT
DADTI
LRCKI
XOE
DRVDD0
DRVSS0
A11
D3
D0
D2
D1
O
O
O
O
—
I
I
I
—
O (3)
O (3)
I
O
O
I
O
O
—
I
I/O
I
—
I
I
I
O
I
I
I
I
O
—
—
O
I/O
I/O
I/O
I/O
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TEL 13942296513
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TEL 13942296513 QQ 376315150 892498299
