— 99 —
Pin No.
Pin Name
I/O
Function
41, 42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
VSS
BCKI
DATAI
LRCKI
INIT
ATT
SHIFT
LATCH
SYSM
NRGCLR
IFSELD
IFSELC
NC
SBCKI
SDATAR
SDATAL
NC
DFDTOL
DFBCKO
DFDTEN
TEST1
TEST2
VSS
—
I
I
I
I
I
I
I
I
I
I
I
—
I
I
I
—
O
O
I
I
I
—
Ground
Bit clock input
Data input
LR clock input
Initialize input
“L”:Reset
Serial data input
Serial shift clock input
Serial latch clock input
External mute signal input
“H”:Active (Fixed at “L”)
N/S calculation section register clear signal input
“H”:Active (Fixed at “L”)
Data line input signal voltage level selection pin (Fixed at “L”)
Control line input signal voltage level selection pin (Fixed at “L”)
Not used
LR clock input (during SCD mode) (Not used)
Bit clock input (during SCD mode) (Not used)
Data input (during SCD mode) (Not used)
Not used
Digital filter serial data Lch output
Digital filter serial data output bit clock output
Digital filter data output
“L”:OFF, “H”:ON
Test pin (Fixed at “L”)
Ground
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