Sony Mavica MVC-FD71, Service Manual, Page: 20 / 79

MVC-FD71
3-7 3-8 3-9
3-3. FDD INTERFACE BLOCK DIAGRAM
37
44
89
91
83
87
92
99
.
7 12 100 3 5 .
.
RST SYS
RAS
HISO
CASL
CASH
WE
OE
AD0 9
29 36
38 45
IC501
FC-66 BOARD
IC807
FLASH MEMORY
DRC
27
32
21
24
.
7
10
2
5.
46
49
.
41
44
.
38
45
29
36
.
18
25
7
8.
RAS
CASL
CASH
WE
OE
A0
A9
A0
A9
D0
D15
DQ0
DQ7
RAS
CASL
CASH
WE
OE
DRAM(16M)
64
66
72
75
58
62
.
CS OSD
HI SO
HI SCK
HI SCK
RSTSYS
RSTSYS
IC705
OSD
HSYNC SYS H
IC503
32
34
24
30
.
BREQ
IC806
A0(HBS)
A01,02
MCD00
MCD15
AD0
AD15
SYSTEM CONTROL
155
162
164
158
.
.
144
142
. 146
152
.
148
PB3
PC3
PB6
PB4
CS2
RO
WR
PC0
PC2
PB1
PB0
PC5
RAS
CASL
CASH
IRQ6
IRQ7
NMI
PB9
EXTAL
XTAL
RXD0
SCK0
RAS
CASL
CASH
D0
D7
D0
D7
B0
B7
62
57
60
.
.
63
.
65
67
.
IC803
SHOCK SENSOR
IC805
SHOCK
SIG DET.
READY
IC802
WR
RD
ENRW
RESET
DMAAK
INT
TC
A0
WE
WPRO
WDATA
RDATA
INDEX
DIR
STEP
TRK0
SIDE
FDD CONTROL
IC801
BUS BUFFER
IC804
5
2
BUFFER
Q601
BUFFER
Q602
BUFFER
Q603
CGR
CS
RST SYS
CS IDIC2
HI SCK
HI SO
RST SYS
CS IDIC2
HI SCK
HI SO
RST SYS
HI SCK
HI SO
IC601
D/A CONV.
VREF PYRA IC301 12
BLOCK
CAMERA
TO
17
16
21
11
13
CN602
56
44
47
51
CN602 CN603 CN602
CN601
50
43
37
55
54
40
39
38
42
41
48
ERASE
R/W A
R/W B
R/W B
R/W A
ERASE
X601
4MHz
SSI
T00
ISTP
IDIR
IDXO
RDO
IWD
WPO
IWG
DCO
RDYO
M ON
DSEL
DIIV
SIDE 1 SEL
TRACK 00
STEP
DIRECTION
INDEX
READ DATA
WRITE DATA
WRITE PROTECT
WRITE GATE
DISK CHANGE
FD READY
MOTOR ON
DRIVE SELECT
X2DD
DISK IN
PANEL G
CN603
PK-43 BOARD
LCD BLOCK
CAY0 7
MCK
IC702 MC CANCEL
MC NMI
96
IC702 50
IC702 99 DR BUS RQ
IC104
IC103 38
IC104 85
IC104 CAC0 7
CA HD IC104 58
IC104 65
IC403 1
CA VD IC104 57
CACVD
CAMERA
BLOCK
TO
MODE CONTROL
BLOCK
TO
8
8
C0
C7
Y0
Y7
HD
VD
XVOC
STRBON STRBON
DR BUS RQ
RAS
CASL
CASH
RST SYS
WE
OE
D0 15
10
16
SYS V
XSCK
MCK
BUS RQ
C0
C3
Y0
Y7
78
81
80
82
53
41
40
SI 45
34
36
35
37
39
42
XCS 44
78
CSIDIC2
43
56
57
MCK
VSYNC
SCLK
S IN
CS
4
20
19
8
1
3
2
15
18
16
17
CGG
CGB
CGBLK
VD
HD
VCK
MCK
SCK
SI
RST
VREF G
VREF B
VREF R
AVDD1
AVDD2
DVDD1
HDO
IOB
IOG
IOR
Y0
Y7
C0
C3
8
4
31
34
45
46
23
19
14
47
6
18
22
21
17
13
D3.2V
L601
48
36
32
1 28
29
26
27
PANEL R
PANEL B
PANEL HD
PANEL VD
SYS V IC702 62
IC702 9
IC702 28
IC702 46
IC702 45
CS OSD IC702 43
BLOCK
MODE CONTROL
TO
10
10
16
16
18
35
34
17
33
X802
15MHz
107
108
3
1
117
116
27
62
61
58
26
28
24
29 RES
2
10
118
IRQ1 119
59
53
57
23
13
11
12
69
10
16
62
WE
OE
SE801
1
2
9 8 7
4
6 3
D4.9V
Q801
1
6
3
5
1
3
6
7
9
13
5
2
75
68
69
71
72
76
42
4
11
10
8
12
18
Q
Q RD
CK
PS S1
VR2
A0 B1 B0
OUT
VCC
1
2
4
30
4
47
46
48
45
69
71
70
51
13
EN
EM2
100
26
11
27
76
8
10
24
36
A01
A02
50
49
42
43
16
82
83
86
D4.9V
L801
X803
16MHz
RSEL
CS
XB1
XA2
XA1
VDD2
VDD1
VDD1
8
4
DISK IN IC702 18
IC702
HISI
44
IC703 4
TO
05
(SEE PAGE 15,18,26,29)
(SEE PAGE 3-6)
(SEE PAGE 3-11)
(SEE PAGE 3-13)
(SEE PAGE 3-6)
(SEE PAGE 3-11)
TO
POWER BLOCK
(SEE PAGE 3-17)
5
17
14
10
11
18
24
6
7
21
22
23
19
20
13
9
5
7
6
4
2
13
12
17
16
11
6
CLOCK
FPTS
HOS
MC
INDEX
PA
PNA
43
47
51
50
48
47
26
28
PB
PNB
STBY
TOS1
DISK
E01
RW1B
RW1A
RW0B
RW0A
E00
OSCO
OSCI
CPO
FPTS
HDS
MC
INDEX
PA0
PA1
PB0
PB1
STBY
TOSI
DISK IN
35
33
22
21
52
IC601
FLOPPY DISK
DRIVE UNIT
FDD INTERFACE
PK-43 BOARD
(SEE PAGE 4-42)
7
3
5
8
1
18
15 20 . 22 25 . 27 29. 31 33
.
@£ REC/PB
1Vp-p
H
$§ REC/PB
3.2Vp-p
V
$∞ REC/PB
3.2Vp-p
H
$¶ REC/PB
3.1Vp-p
H
!ª
REC/PB
0.8Vp-p
H
#¶
-
$¢
REC/PB
3.2Vp-p
0.025
µ
sec
!¢
REC/PB
1Vp-p
H
*£ REC/PB
3.2Vp-p
16MHz
PB
3.2Vp-p
15MHz
107
$™ REC/PB
5Vp-p
4MHz
21
DISK IN