Sony KDL-32U2520, Service Manual

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11
21
22
R Q P EE FF S T
U
V W X
Y Z AA BB CC
DD
20
18
19
17
15
16
14
12
13
XX
FB5647
JL5657 JL5659
JL5662
JL5655 JL5656
JL5647 JL5646 JL5644 JL5642
NAND_ALE,NAND_CLE,NAND_RBB
JL5651
RADD[19-25]
RADD[0-14]
XX
R5660
XX
R5661
M
1
7
J
9
J
1
0
J
1
1
J
1
2
J
1
3
K
9
K10
K11
K12
K13
L
9
L
1
0
L
1
1
L
1
2
L
1
3
M
9
M
1
0
M
1
1
M
1
2
M
1
3
N
9
N10
N11
N12
N
P2 G2 R2 G1 K3 V1 C1 Y1 P3 B1 E4 F2 H1 R1 R3 T1 T3 U1 D1 D2 C3 U2 R4 V2
W2
V4 C2 D4 E2
J1
G3
J4
K4 L2
M2
N2 L4
M4
J3
H3
M1
N1 K1 N3 T2
M3
L3 H4 G4
J2
H2 F1 E3 E1 D3 V3 K2 L1 P1 T4
W1
U3 U4
AA18
Y18
Y2 P4 F3
AA11
Y10
V7
M21 N17
IC5630
XX
IOWRB / PPORT31 IORDB / PPORT30
P2
INPACKB / PPORT33
G2
GPIO_VS1B / PPORT28
R2
GPIO_RESET / PPORT32
G1
GPIO_IREQB / PPORT24
K3
GPIO_CD1B / PPORT26
V1
GPIO_CD2B / PPORT35
C1
PCE1B(CE2B_2) / PPORT36
Y1
PCE0B(CE2B_1) / PPORT27
P3
IOSI16B / PPORT25
B1
STP1_STRT / PPORT38
E4
STP1_EN / PPORT37
F2
STP1_CLK / PPORT29
H1
RDATA15 / STP1_DAT7 / BOOT_NAND_SEL1
R1
RDATA14 / STP1_DAT6 / BOOT_NAND_SEL0
R3
RDATA13 / STP1_DAT5 / BOOTSEL1
T1
RDATA12 / STP1_DAT4 / BOOTSEL0
T3
RDATA11 / STP1_DAT3 / MINIBOOT
U1
RDATA10 / STP1_DAT2 / BWSEL
D1
RDATA9 / STP1_DAT1 / ROMBEND
D2
RDATA8 / STP1_DAT0 / MCLKSEL2
C3
RDATA7 / MCLKSEL1
U2
RDATA6 / MCLKSEL0
R4
RDATA5 / VRCLKSEL1
V2
RDATA4 / VRCLKSEL0
W2
RDATA3
V4
RDATA2 / MRGMODE1
C2
RDATA1 / MRGMODE0
D4
RDATA0 / ENDIAN
E2
RADD25 / HSD7 / EJTAG_MODE
J1
RADD24 / HSD6 / DINT_EN
G3
RADD23 / HSD5 / DSYSELB
J4
RADD22 / HSD4 / PCI_MODE
K4
RADD21 / HSD3 / PCI_SIZE1
L2
RADD20 / HSD2 / PCI_SIZE0
M2
RADD19 / HSD1 / NAND_CS
N2
RADD18 / HSD0
L4
RADD17 / PKTSTRT
M4
RADD16 / HSDE
J3
RADD15 / HSDCLK
H3
RADD14
M1
RADD13
N1
RADD12
K1
RADD11
N3
RADD10
T2
RADD9
M3
RADD8
L3
RADD7
H4
RADD6
G4
RADD5
J2
RADD4
H2
RADD3
F1
RADD2
E3
RADD1
E1
RADD0
D3
FCSB1
V3
FCSB0
K2
FWEB
L1
FOEB
P1
NSEB
T4
NRBB
W1
NCLE
U3
NALE
U4
GCSB3 / PPORT50
AA18
GCSB2 / PPORT49
Y18
GCSB1
Y2
GCSB0
P4
GRDYB
F3
RSTSWB
AA11
RSTOUT
Y10
PWMOUT
V7
CLK27IN
M21
AVDDP
N17
AGNDP
M17
GND
J9
GND
J10
GND
J11
GND
J12
GND
J13
GND
K9
GND
K10
GND
K11
GND
K12
GND
K13
GND
L9
GND
L10
GND
L11
GND
L12
GND
L13
GND
M9
GND
M10
GND
M11
GND
M12
GND
M13
GND
N9
GND
N10
GND
N11
GND
N12
GND
IN_TSD[0-7]
RDATA[0-15]
INPACKB
FWEB
CARD_RESET
CE1B
VS1B
IORDB
IOIS16B
FCSB0
FOEB
nMASTER_RESET
CD2B
PWMOUT
CLK27M
IREQB
nCI_WAIT
CD1B
XX
C5669
XX
C5667
XX
C5668
XX
C5666
+1V5D
BUF_MDO_STRT
BUF_MDO_EN
BUF_MDO_CLK
XX
R5624
XX
R5625
RESET_N
XX
R5626
RADD[22] RADD[23] RADD[24] RADD[25] RADD[20] RADD[21] RADD[19]
NAND_ALE NAND_CLE NAND_RBB NAND_SEB
RADD[0] RADD[1] RADD[2] RADD[3] RADD[4] RADD[5] RADD[6] RADD[7] RADD[8] RADD[9] RADD[10] RADD[11] RADD[12] RADD[13] RADD[14]
RDATA[7] RDATA[6] RDATA[5] RDATA[4] RDATA[3] RDATA[2] RDATA[1] RDATA[0]
RDATA[15] RDATA[14] RDATA[13] RDATA[12] RDATA[11] RDATA[10] RDATA[8] RDATA[9]
THIS CAPACITOR TO BE PLACED UNDERNEATH BGA
ALL JIG LANDS TO BE PLACED ON SIDE B
BDTR-2
1D/9 MAIN MICRO CONTROLLER, PANEL DRIVING, AUDIO & VIDEO PROCESSOR
BDTR-2.SE1
~ BDTR-2 Board Schematic Diagram [ Main Microcontroller, Panel Driving, Audio & Video Processor ] Page 1D/9 ~