Sony ICF-M88B - S2 Sports Bicycle Radio, Service Manual

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15
ICF-M88B
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IC Pin Function Description
KEY BOARD IC101
µ
PD789488GC-A35-8BT (SYSTEM CONTROLLER)
Pin No. Pin Name I/O Description
1, 2 CAPH, CAPL — Terminal for doubler circuit capacitor connection to develop liquid crystal display drive voltage
3 to 5 VLC2 to VLC0 — Terminal for doubler circuit capacitor connection to develop liquid crystal display drive voltage
6 to 9 COM0 to COM3 O
Common drive signal output to the liquid crystal display
10 to 35 S0 to S25 O
Segment drive signal output to the liquid crystal display
36, 37 P86, P87 O Not used
38
AVDD — Power supply terminal (+2.41V) (for A/D converter)
39
VERSION I Setting terminal for the destination Fixed at “H” in this set
40 to 46 P66 to P60 I Not used
47 AVSS — Ground terminal (for A/D converter)
48 VDET2 I Voltage detection signal input terminal “L”: 2.1V or less
49 VDET1 I Voltage detection signal input terminal “L”: 1.9V or less
50
BEEP O Beep sound output to the FM/AM front-end
51 PS I Pulse signal input terminal for 1 rotation time measurement
52 MOUNT I Mount state detection signal input terminal “L”: mount connected, “H”: no connected
53 MUTE O Radio output muting on/off control signal output terminal “L”: muting on
54
P24 O
Not used
55 DATA/EEPROM I/O Two-way data bus with the EEPROM
56 CLK/EEPROM O Serial clock signal output to the EEPROM
57 DATA/PLL O Serial data output to the FM/AM PLL
58 CLK/PLL O Serial clock signal output to the FM/AM PLL
59 CE/PLL O Chip enable signal output to the FM/AM PLL
60, 61 P10, P07 O
Not used
62 POWER O Radio power on/off control signal output terminal “H”: power on
63
LED O
LED drive signal output of the liquid crystal display back light “L”: LED on
64 KR3 I Key return signal input terminal Not used
65 to 67 KR2 to KR0 I Key return signal input terminal
68 P00 O
Not used
69 IC0 — Connected to the ground
70 XT1 I Sub system clock input terminal (32.768 kHz)
71 XT2 O Sub system clock output terminal (32.768 kHz)
72
VDD — Power supply terminal (+2.4V)
73 VSS — Ground terminal
74 X1 I Main system clock input terminal (4.19 MHz)
75 X2 O Main system clock output terminal (4.19 MHz)
76 RESET I
System reset signal input from the reset signal generator “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
77 SHIFT O Shift clock on/off control signal output terminal “L”: shift clock on
78 to 80 KS2 to KS0 O Key source signal output terminal