5-46
HVR-1500
5-46
2
3
4
5
A
B
C
D
E
F
G
H
1
DVP-42 (11/14)
SUFFIX: -11
DVP-42 (11/14)
SUFFIX: -11
DV Video/Audio Digital Process
DVP-42 (11/14)
BOARD NO. 1-870-497-11
BIX-167_DVP-42_010_11
TC7WH08FU(TE12R)
IC1105
(3/3)
4
GND
8
VCC
TC7WH32FU(TE12R)
IC1106 (3/3)
4
GND
8
VCC
XSAVER_CFG_END
008
XHPR_CFG_END
014
XSDI_CFG_END
014
SDI_EXIST
013,014
GND
GND
GND
GND
+3V
+3V
+3V
+3V
SDI_CFG_START
014
DVP_CFG_END
013
FPGA_XCLR
008,009,010,011
TC7WH08FU(TE12R)
IC1105 (2/3)
5
6
3
TC7WH32FU(TE12R)
IC1106 (2/3)
5
6
3
TC7WH32FU(TE12R)
IC1106 (1/3)
1
2
7
TC7WH08FU(TE12R)
IC1105 (1/3)
1
2
7
GND
GND
GND
AVANT_nCONFIG
011
AVANT_DCLK
011
AVANT_EPC_ASD
011
AVANT_EPC_CS
011
Angle type
CN1101
1
VCC/VCC
2
DATA_OUT/TRST
3
ASDI/TDI
4
CONF_DONE/TDO
5
nCONFIG/TMS
6
DCLK/TCK
11
GND
12
GND
7
MODE(L)/(MODE)
8
GND/GND
9
nCE/(NC)
10
nCS/(NC)
AVANT_DATA0
011
AVANT_nCE
011
AVANT_CONF_DONE
011
GND
AVANT_EPC_CS
011
+1.5V
GND
GND
AVANT_nCE
011
GND
GND
GND
AVANT_EPC_ASD
011
GND
AVANT_CONF_DONE
011
CL1104
AVANT_nCONFIG
011
GND
CL1103
AVANT_DATA0
011
+1.5V
AVANT_DCLK
011
GND
CL1102
GND
TC7SZ125FU(TE85R)
IC1109 (1/2)
2
1
4
TC7SZ125FU(TE85R)
IC1109
(2/2)
3
GND
5
VCC
GND
+3V
+3V
AVANT_CFG_START
011
0
R1122
10k
R1123
TC7SZ125FU(TE85R)
IC1111 (1/2)
2
1
4
TC7SZ125FU(TE85R)
IC1111
(2/2)
3
GND
5
VCC
SAVER_CFG_START
009
+3V
FPGA_XCLR
008,009,010,011
GND
+3V
+3V
0
R1126
+3V
0
R1129
0
R1130
+3V
10k
R1108
0
R1102
NM
0
R1104
NM
0
R1105
NM
0
R1106
NM
0
R1107
NM
0
R1109
NM
0
R1103
NM
EP1C12F324C8N(300)
(4/4)
IC1001
76
nCONFIG[J2]
11
DCLK[L1]
300
nSTATUS[L12]
106
CONF_DONE[K17]
290
DATA0[H7]
9
IO4/nCSO[J1]
129
IO88/LVDS23p/INIT_DONE[C3]
130
IO89/LVDS22p/CLKUSR[D3]
265
IO212/ASDO[K6]
77
nCEO[K2]
291
nCE[J7]
43
TCK[K18]
107
TDI[J17]
278
TDO[K13]
247
TMS[K14]
136
MSEL0[K3]
292
MSEL1[K7]
229
VCCA_PLL1[J5]
10
GNDA_PLL1[K1]
264
GNDG_PLL1[J6]
302
VCCA_PLL2[J12]
301
GNDA_PLL2[K12]
44
GNDG_PLL2[J18]
6
IO1/DPCLK1/DQS0L[F1]
111
IO71/DPCLK4/DQS0R[E17]
135
CLK0/LVDSCLK1p[J3]
162
CLK3/LVDSCLK2n[J16]
169
IO125/LVDS47n/DQ0T2[C15]
183
IO139/LVDS18p[F4]
192
IO147/DPCLK7/DQS1B[R4]
204
IO159/DPCLK5/DQS1R[P15]
208
IO163/PLL2_OUTp[K15]
209
CLK2/LVDSCLK2p[J15]
226
IO180/LVDS18n[F5]
228
IO182/LVDS12n/DM0L[H5]
230
IO183/PLL1_OUTn[K5]
234
IO187/DPCLK0/DQS1L[P5]
253
IO203[E13]
255
IO204[E11]
256
IO205/VREF1B2[E10]
258
IO206/LVDS32n/DQ1T0[E8]
261
IO209/LVDS16p[F6]
262
IO210/LVDS14n/DQ0L6[G6]
263
IO211/VREF1B1[H6]
266
IO213/LVDS11n[L6]
269
IO216/LVDS5n[N7]
270
IO217/LVDS101n[N8]
271
IO218/LVDS89n[N9]
272
IO219/LVDS80p[N10]
273
IO220/LVDS77p[N11]
274
IO221/LVDS70p[N12]
275
IO222/LVDS70n[N13]
276
IO223/LVDS65n[M13]
277
IO224/LVDS65p[L13]
279
IO225/LVDS63n[J13]
280
IO226/LVDS63p/DM0R[H13]
281
IO227/LVDS59n/DQ0R4[G13]
282
IO228/LVDS55n[F13]
283
IO229/LVDS57p[F12]
284
IO230/LVDS49p[F11]
285
IO231/LVDS46p[F10]
286
IO232/LVDS37p[F9]
287
IO233/LVDS25n[F8]
288
IO234/LVDS16n[F7]
293
IO235/LVDS11p/DM1L[L7]
295
IO236/LVDS101p[M8]
296
IO237/LVDS89p[M9]
297
IO238/LVDS80n[M10]
298
IO239/LVDS77n[M11]
304
IO240/LVDS57n[G12]
305
IO241/LVDS49n[G11]
306
IO242/LVDS46n[G10]
307
IO243/LVDS37n[G9]
308
IO244/LVDS25p[G8]
324
GND28[J10]
322
GND27[K9]
320
GND26[H9]
318
GND25[H11]
317
GND24[J11]
316
GND23[K11]
315
GND22[L11]
314
GND21[L10]
312
GND20[L8]
311
GND19[K8]
310
GND18[J8]
309
GND17[H8]
114
GND16[B17]
99
GND15[U17]
84
GND14[U2]
69
GND13[B2]
67
GND12[A3]
54
GND11[A16]
52
GND10[A18]
50
GND9[C18]
37
GND8[T18]
35
GND7[V18]
33
GND6[V16]
20
GND5[V3]
18
GND4[V1]
16
GND3[T1]
3
GND2[C1]
1
GND1[A1]
240
VCCIO4_4[P11]
237
VCCIO4_3[P8]
31
VCCIO4_2[V14]
22
VCCIO4_1[V5]
303
VCCIO3_4[H12]
299
VCCIO3_3[M12]
48
VCCIO3_2[E18]
39
VCCIO3_1[P18]
257
VCCIO2_4[E9]
254
VCCIO2_3[E12]
65
VCCIO2_2[A5]
56
VCCIO2_1[A14]
294
VCCIO1_4[M7]
289
VCCIO1_3[G7]
14
VCCIO1_2[P1]
5
VCCIO1_1[E1]
323
VCCINT12[K10]
321
VCCINT11[J9]
319
VCCINT10[H10]
313
VCCINT9[L9]
68
VCCINT8[A2]
53
VCCINT7[A17]
51
VCCINT6[B18]
36
VCCINT5[U18]
34
VCCINT4[V17]
19
VCCINT3[V2]
17
VCCINT2[U1]
2
VCCINT1[B1]
10k
R1120
47k
R1101
47k
R1121
47k
R1124
47k
R1125
47k
R1127
47k
R1128
FB1101
6.8uH
L1101
FB1102
22
R1112
22
R1113
22uF
C1141
22uF
C1140
GND
0
R1111
NM
AVANT_TDI
011
GND
AVANT_TDO
009,011
0
R1140
AVANT_TMS
011
0
R1115
NM
0
R1119
0
R1116
NM
AVANT_CONF_DONE
011
0
R1139
AVANT_STATUS
011
10k
RB1101
12
34
56
78
AVANT_DATA0
011
AVANT_TCK
011
0
R1117
EPC2LC20N-TP
IC1102
DCLK
4
OE
8
nCS
9
VCCSEL
5
VPPSEL
14
TDI
11
TDO
1
TMS
19
TCK
3
GND
10
VPP
18
VCC
20
nCASC
12
DATA
2
nINIT_CONF
13
0
R1114
GND
AVANT_DCLK
011
0
R1110
0
R1131
NM
0
R1132
NM
0
R1133
NM
0
R1134
NM
0
R1135
NM
0
R1136
NM
0
R1137
NM
47k
R1138
AVANT_TDI
011
AVANT_TCK
011
AVANT_TDO
009,011
AVANT_TMS
011
AVANT_STATUS
011
+3V-B
+3V-B
+3V-B
+3V-B
+3V-B
+3V-B
0
R1141
0
R1142
0
R1143
47k
R1144
+3V
CL1105
CL1107
CL1108
CL1109
CL1110
CL1111
CL1112
CL1113
CL1115
TC7WH123FU(TE12R)
IC1112
RX/CX
7
Q
5
CLR
3
GND
4
VCC
8
CX
6
A
1
B
2
TC7SH04FU(T5RSOYJF)
IC1113 (1/2)
2
4
TC7SH04FU(T5RSOYJF)
IC1113 (2/2)
3
GND
5
VCC
TC7SH08FU(T5RSOYJF)
IC1114 (1/2)
2
1
4
TC7SH08FU(T5RSOYJF)
IC1114 (2/2)
3
GND
5
VCC
1uF
C1142
470k
R1145
1SS400TE-61
D1001
0
R1146
NM
DVP_CFG_START
013
+3V
GND
GND
GND
GND
+3V
+3V
AVANT_CFG_START
011
CL1101
CL1116
CL1117
CL1118
10k
R1118
0.1uF
C1103
0.1uF
C1105
0.1uF
C1135
0.1uF
C1104
0.1uF
C1144
0.1uF
C1143
0.1uF
C1101
0.1uF
C1145
0.1uF
C1102
NM
0.1uF
C1137
0.1uF
C1139
10V B
0.1uF
C1116
10V
B
0.1uF
C1119
10V B
0.1uF
C1107
10V B
0.1uF
C1117
10V
B
0.1uF
C1127
10V
B
0.1uF
C1122
10V
B
0.1uF
C1125
10V
B
0.1uF
C1108
10V
B
0.1uF
C1124
10V
B
0.1uF
C1123
22uF
C1106
10V
B
0.1uF
C1126
10V
B
0.1uF
C1131
10V B
0.1uF
C1110
10V
B
0.1uF
C1120
10V
B
0.1uF
C1109
10V
B
0.1uF
C1121
10V B
0.1uF
C1111
10V
B
0.1uF
C1128
10V B
0.1uF
C1112
10V B
0.1uF
C1115
10V B
0.1uF
C1114
10V B
0.1uF
C1113
10V
B
0.1uF
C1129
10V
B
0.1uF
C1118
DCV_27M_AVANT
014
VILL_SPARE
014
HDV_AU_BUS
010,014
+3V
+3V
NSG_CK27D_AVANT
013
SN74LVC3G04DCUR
IC1107 (1/4)
1
7
SN74LVC3G04DCUR
IC1107 (2/4)
6
2
SN74LVC3G04DCUR
IC1107 (3/4)
3
5
SN74LVC3G04DCUR
IC1107 (4/4)
4
GND
8
VCC
EPCS4SI8N(15ST)
IC1101 NM
ASDI
5
VCC2
7
DATA
2
DCLK
6
CS
1
GND
4
VCC1
3
VCC3
8
0
R1147
0
R1148
0
R1149
SAVER_TDO
009
SAVER_TMS
009
SAVER_TCK
009
HDV_256FS
To FPGA
To FPGA
Connect FPGA K17 pin
Connect FPGA H7 pin
Connect FPGA J2 pin
Connect FPGA L1 pin
FPGA_DATA0 (2.5V IF)
MSEL1 = GND
Connect FPGA K6 pin
MSEL0 = GND
Connect FPGA J1 pin
ALTERA_AS / ALTERA_PS
From FPGA
To FPGA
Connect FPGA J7 pin
AS MODE (20MHz:EPCS4)
EPR2
AVANT2(4/4)
MSEL0 = +3V
MSEL1 = GND
PS MODE
AVANT2
Summary of Contents for HDV HVBK-1505
Page 5: ...3 J HVR 1500 ...
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Page 101: ...3 1 J HVR 1500 ...
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Page 103: ...3 1 E HVR 1500 Section 3 Circuit Description This section is published one of these days ...
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Page 251: ...6 7 HVR 1500 6 7 DDE 22 DDE 22 DDE 22 B SIDE SUFFIX 11 FOR HVBK 1505 ...
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Page 263: ...6 19 HVR 1500 6 19 CN61 CN71 CN72 CN73 CN81 CN82 MB 1098 MB 1098 MB 1098 B SIDE SUFFIX 11 ...
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Page 274: ...Printed in Japan Sony Corporation 2007 4 08 2007 HVR 1500 J HVR 1500 SY J E 9 968 317 01 ...