Sony HDV HVBK-1505, (Japanese) Service Manual

Page: 112 / 274

4-8 4-8
HVR-1500
DDE-22 DDE-22
DDE-22
(HVBK-1505)
Y/S-Y/CPST
CN1
VIDEO IN
VIDEO IN
R-Y/S-C
B-Y
VIDEO IN
75
IC102
1
5
7
6
Q105
BUFF LPF
5
AMP
1
IC107
SYNC SEP
SW
GAIN
Q110
BUFF
Q104
3
TP101
INPUT VIDEO
BUFF
IC107
TP102
A/D CPST/S-Y/Y
7
RV102
CPST/S-Y/Y
LEVEL
H PAL
L COMPOSITE
Q107 Q108
SIGNAL DET
118
16
Q107
BUFF
6
7
5
1
IC101
BUFF
Q106
L COMPONENT
3
Q111
GAIN
SW
IC108
AMP
LEVEL
S-C/R-Y
RV103
7
A/D S-C/R-Y
TP103
IC108
BUFF
1 5
LPF
116
BUFF
Q101
RV101
S-C LEVEL
BUFF
Q103
AMP
IC106
3
LPF
5 1
BUFF
IC106
TP104
A/D B-Y
7
RV104
B-Y LEVEL
108
AIN00
AIN10
AIN20
A/D & VIDEO DEC
IC105
VDEC
SVO9-0
49
SCK
SVS
40
36
SFLD
SVB
38
39
SHB
SHS
41
XTLI
82
VCXO
84
21
SDA
IRQ N
18
20
SCL
RST N
90
96
TRST N
ANA H
ANA HBLK
ANA VBLK
ANA F
ANA V
DECCK27
VCO
X101 27MHz
SDA
SCL
GPCL
XV750 RST
72
70
66
71
69
68
CLK2
XVIC
IC202
75
74
73
4 1
IC203
Q204
IC204
2
5
6
3
H PAL
L COMPOSITE
L COMPONENT
41
42
40
D204
NTSC
9
5,14
1,12
4,11
2,15
10
IC400
10 10 ANADT9-0 ADYC9-0 10
AFC CK27
SEL SYNC 38
37
9
7
10
IC211
IC211
13
11 SELECT SYNC
AFC CK27
10 ADYC9-0
6 2
IC208
SG SYNC 39
10 4
IC200
2
OSC
97 SY SI
98 SY SO
SY SCK 99
100 SY XVIC CS
17
16
18 2
4
3
2
IC213
6
XVIC CS
SY SCK
SY SO 3V
SY SI 3V
IC212
7
5 3
1
XVIC CLR 5
2 6
IC215
JC RESET
FPGA RESET2
92 NTSC PAL 1,2 4
IC216
21-105
21-106
21-93
21-147
21-138
21-137
21-139
21-136
21-143
21-131
21-141
21-8
21-7
SSS:52-92
SSS:52-91
SSS:52-33
SSS:52-90
SSS:52-48
SSS:52-49
SSS:51-60
SSS:52-34
SSS:51-59
SSS:52-60
AVP:5-105
AVP:5-106
AVP:5-93
DVP:1- 21-
81
90 90
81
DDE ID0
DDE ID1
DDE EXIST
Q203 4
D203
VCXO H LOCK
VCXO SC LOCK
D204
3 Q202
Q200 1
D200
NON INTER
NON STD D201
2 Q201
SSS:51-82 21-142
IC212
12 8 DONE 65
Q205
21-146 SSS:52-95
CONFIG START2
CONFIG END4
17
7
16
6
60
8
13
ASDO
DATA
DCLK
nCSO
DONE
nCONFIG
nCE
CS
DCLK
DATA
ASDI
(FLASH)
CONFIG ROM
IC206
2
5
DELAY
1
6
IC217,219
200-2
200-1
200-3
200-6
200-4
200-5
200-10
200-9
DATA OUT
ASDO
nCSO
DCLK
DONE
nCONFIG
nCE
+3V VCC
ASDI
nCS
CONF DONE
7
14 158
155
21- PS:100-
REG +6V 6
IC303
4
+5V REG
PS301
+5V-2
+4.9V
+4.9V REG
IC300,Q300
+5V REG
+5V-3
IC300,Q301
IC301
-5VREG
IC300,Q302
6
IC302
2,5
-5V REG
PS302
REG -6V
PS:100- 21-
121
122
24
17
-5V
-5V-2
37
44
21- PS:100-
REG +5V
PS303
+3.3V
+3.3V REG
5
IC103
4
+5V
+3V
4
IC201
5
+1.5V REG
+1.5V
REG +3.15V
PS:100- 21-
151
154 34
27
PS300
+2.5V
+2.5V REG
6
IC104
4
IC105 VENC
IC202 XVIC
CN400
AUDIO IN
1/3
IC402
AMP
3 1
5 7
2 6
1
3
2
B A
0
3,13
LEVEL SEL
X
Y
CH1 A/D
AMP
IC502
6
5
7
X
Y
IC502
AMP
1 3
HEADROOM SEL
3,13
0
A B
2
3
1
IC504
10
2,15
4,11
1,12
5,14
9
IC506
AMP
6
7
1
7
6
20
18
12
16 +4dB
0
-6
-3
1
7
6
AMP
IC507
9
5,14
1,12
4,11
2,15
10
IC505
1
3
2
B A
0
3,13
HEADROOM SEL
3 1
AMP
IC503
Y
X
7
5
6
IC503
AMP
A/D
Y
X
LEVEL SEL
3,13
0
A B
2
3
1
6 2
7 5
1 3
AMP
IC403
2/4
AUDIO IN
CN401
IC401
10
2,15
4,11
1,12
5,14
9
2
1
AINR+
AINR-
AINL-
AINL+
IC508 A/D
IC404
9 11
4 1,2
IC404
IC501
15 5
14 6
8
7 13
12
21-111
21-112
21-113
21-114
21-110
21-109
AU CH2 IN LEVEL SEL2
AU CH1 IN LEVEL SEL2
AU CH2 IN LEVEL SEL1
AU CH1 IN LEVEL SEL1
AU HEAD ROOM SEL2
AU HEAD ROOM SEL1
21-117
21-118
21-116
AVP:5-118
AVP:5-117
AVP:5-116
16
17
18
19
18
17 2
3
4
IC404
AU REC LRCK
AU REC BCK
AU REC 256FS
AVP:5-114
AVP:5-109
AVP:5-110
AVP:5-113
AVP:5-112
AVP:5-111
2 6
IC209
AU REC DT12 21 12
REC DT
AU
21-115 AVP:5-115
AU JC RESET
Q500
16
PD
LRCK
SCLK
MCLK
SDATA
ANADT9-0
DECCK27
ANA V
ANA F
ANA VBLK
ANA HBLK
ANA H
GPCL
SCL
SDA
CLK0
X200
27MHz
XV750 RST
AU JC RESET
IC200
DVP:1-93
1
(XNTSC)
SPARE4
NC
CH2
NSG SYNC
12
11
CN200
(FPGA)
VIDEO
PROC