Sony HDV HVBK-1505, (Japanese) Service Manual

Page: 172 / 274

5-44
HVR-1500
5-44
2
3
4
5
A B C D E F G H
1
DVP-42 (9/14)
SUFFIX: -11
DVP-42 (9/14)
SUFFIX: -11
DV Video/Audio Digital Process
DVP-42 (9/14)
BOARD NO. 1-870-497-11
BIX-167_DVP-42_010_09
GND
+1.5V
GND
GND
GND
GND
GND
GND
+1.5V
GND
GND
GND
Angle type
CN901
1 VCC/VCC
2 DATA_OUT/TRST
3 ASDI/TDI
4 CONF_DONE/TDO
5 nCONFIG/TMS
6 DCLK/TCK
11
GND
12
GND
7 MODE(L)/(MODE)
8 GND/GND
9 nCE/(NC)
10 nCS/(NC)
SAVER_nCONFIG 009
SAVER_nCE 009
SAVER_DCLK 009
SAVER_EPC_CS 009
GND
SAVER_DATA0 009
SAVER_CONF_DONE 009
SAVER_EPC_ASD 009
GND
GND
GND
P_TIMING
002,004,005,007,008,013,014
P_ERROR_JIG 004
P_TTRCK_JIG
002
+5V
+3V
+5V
GND
CN902
1 +5V
2 TRKT
3 C1ERP
4 SYNC DET
5 ER SER
6 GND
7 TTRCK
8 XPLD_RESET
9 GND
10 REG +3V
11 REG +3V
12 13
GNDGND
SAVER_EPC_CS 009
SAVER_EPC_ASD 009
SAVER_DCLK 009
SAVER_nCE 009
SAVER_CONF_DONE 009
SAVER_nCONFIG 009
SAVER_DATA0
009
CL902
CL903
CL904
JC_RESET 013,014
XCLR1
001,003,005,006
GND
+3V
XCLR2
002,004,005,007
GND
15pF
C905
18MHz
X901
22
R916
1M
R905
15pF
C904
GND
TC7SHU04FU(T5RSOJF)
IC902
GND
3
VCC
5
A
2
Y
4
NC
1
GND
TCK18 008
390
R910
SAVER_CFG_START 011
0
R930
10k
R931
0
R932
TRCK 014
0
R933
0
R934
+3V
10k
R914
0 R907 NM
0 R908 NM
0 R909 NM
0 R912 NM
0
R915
NM
0
R906
NM
FPGA_CLR2 013,014
10k
R935
+3V
GND
FPGA_XCLR
10k
R929
10V B
0.1uF
C916
10V B
0.1uF
C921
10V
B
0.1uF
C931
10k
R927
10V B
0.1uF
C920
10V
B
0.1uF
C928
10V B
0.1uF
C924
10V B
0.1uF
C909
FB901
10k
R921
22
RB901
1 2
3 4
5 6
7 8
10k
R926
22uF
C934
10V
B
0.1uF
C930
FB902
10V
B
0.1uF
C933
10V
B
0.1uF
C927
10V
B
0.1uF
C922
10V
B
0.1uF
C910
22uF
C908
10V B
0.1uF C919
10V B
0.1uF C917
22uF
C932
10V B
0.1uF
C926
10V B
0.1uF
C925
10V B
0.1uF
C911
10V B
0.1uF C914
10V B
0.1uF C915
10V B
0.1uF
C923
10V B
0.1uF C918
10k
R913
10V
B
0.1uF
C929
10V B
0.1uF C912
22
R919
22
R920
SN74LVC3G04DCUR
IC904 (2/4)
6 2
SN74LVC3G04DCUR
IC904 (1/4)
1 7
SN74LVC3G04DCUR
IC904 (3/4)
3
5
SN74LVC3G04DCUR
IC904 (4/4)
4
GND
8
VCC
0
R937
NM
0 R938
NM
0
R939
NM
0 R940
NM
0 R941
NM 0 R942
NM
EPC2LC20N-TP
IC905
DCLK
4
OE
8
nCS
9
VCCSEL
5
VPPSEL
14
TDI
11
TDO
1
TMS
19
TCK
3
GND
10
VPP
18
VCC
20
nCASC
12
DATA
2
nINIT_CONF
13
0 R943
0 R944
0 R945 NM
0 R946
0 R947
10k
RB902
12 34 56 78
SAVER_DATA0 009
0
R948
GND
GND
SAVER_TDI 009
SAVER_TDO 009,011
SAVER_TMS 009,011
SAVER_TCK 009,011
SAVER_DCLK 009
SAVER_STATUS
009
SAVER_CONF_DONE 009
0 R949
0 R950
0 R951
0
R953
NM
SAVER_STATUS 009
SAVER_TDI 009
SAVER_TCK 009,011
SAVER_TMS
009,011
SAVER_TDO 009,011
GND
47k
R952
+3V-A
+3V-A
+3V-A +3V-A +3V-A
+3V-A
+3V-A
EP1C12F324C8N(300)
(2/2) IC805
76
nCONFIG[J2]
11
DCLK[L1]
300
nSTATUS[L12]
106
CONF_DONE[K17]
290
DATA0[H7]
9
IO4/nCSO[J1]
129
IO88/LVDS23p/INIT_DONE[C3]
130
IO89/LVDS22p/CLKUSR[D3]
265
IO212/ASDO[K6]
77
nCEO[K2]
291
nCE[J7]
43
TCK[K18]
107
TDI[J17]
278
TDO[K13]
247
TMS[K14]
136
MSEL0[K3]
292
MSEL1[K7]
229
VCCA_PLL1[J5]
10
GNDA_PLL1[K1]
264
GNDG_PLL1[J6]
302
VCCA_PLL2[J12]
301
GNDA_PLL2[K12]
44
GNDG_PLL2[J18]
324
GND28[J10]
322
GND27[K9]
320
GND26[H9]
318
GND25[H11]
317
GND24[J11]
316
GND23[K11]
315
GND22[L11]
314
GND21[L10]
312
GND20[L8]
311
GND19[K8]
310
GND18[J8]
309
GND17[H8]
114
GND16[B17]
99
GND15[U17]
84
GND14[U2]
69
GND13[B2]
67
GND12[A3]
54
GND11[A16]
52
GND10[A18]
50
GND9[C18]
37
GND8[T18]
35
GND7[V18]
33
GND6[V16]
20
GND5[V3]
18
GND4[V1]
16
GND3[T1]
3
GND2[C1]
1
GND1[A1]
240
VCCIO4_4[P11]
237
VCCIO4_3[P8]
31
VCCIO4_2[V14]
22
VCCIO4_1[V5]
303
VCCIO3_4[H12]
299
VCCIO3_3[M12]
48
VCCIO3_2[E18]
39
VCCIO3_1[P18]
257
VCCIO2_4[E9]
254
VCCIO2_3[E12]
65
VCCIO2_2[A5]
56
VCCIO2_1[A14]
294
VCCIO1_4[M7]
289
VCCIO1_3[G7]
14
VCCIO1_2[P1]
5
VCCIO1_1[E1]
323
VCCINT12[K10]
321
VCCINT11[J9]
319
VCCINT10[H10]
313
VCCINT9[L9]
68
VCCINT8[A2]
53
VCCINT7[A17]
51
VCCINT6[B18]
36
VCCINT5[U18]
34
VCCINT4[V17]
19
VCCINT3[V2]
17
VCCINT2[U1]
2
VCCINT1[B1]
10V B
0.1uF C913
22
R954
0.1uF
C939
0.1uF
C941
0.1uF
C906
0.1uF
C907
NM
6.8uH
L901
+3V
6.8uH
L902
+3V
DTC144EE-TL
Q901
DTC144EE-TL
Q904
DTC144EE-TL
Q902
DTC144EE-TL
Q903
C
4.7uF
C903
EPCS4SI8N(15ST)
IC903
NM
ASDI
5
VCC2
7
DATA
2
DCLK
6
CS
1
GND
4
VCC1
3
VCC3
8
0
R955
AVANT_TDO 011
C1ERP
P_TRKT
X_ER_SER
X_SYNC_DET
SAVER2(2/2)
Connect FPGA J2 pin
MSEL1 = GND
To FPGA
Connect FPGA L1 pin
Connect FPGA J7 pin
Connect FPGA J1 pin
Connect FPGA H7 pin Connect FPGA K6 pin
EPR2
MSEL0 = GND
Connect FPGA K17 pin
ALTERA_AS / ALTERA_PS
AS MODE (20MHz:EPCS4)
To FPGA
To FPGA
CN902
system reset
MSEL1 = GND
MSEL0 = +3V
PS MODE SAVER2
008,010,011