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30
30
7.
IC BLOCK DIAGRAMS
– MB BOARD –
IC001
PLL1700E/2K
OSC
PLL1
COUNTER P
RESET
8
7
9
20 19
18
17
COUNTER Q
14
16
15
1
2
5
6
3
4
MODE
CONTROL
I/F
PLL2
PLL1
13
12
11
10
MC/FS1
MD/FS0
RST
SCKO3
SCKO2
VDDB
GNDB
SCKO4
SCKO1
MCKO
VDDP
GNDP
RSV
ML/SR0
MODE
XT2
XT1
VDD
GND
MCKO
IC902, 905 – 907
CXD8799N-T2
4
5
6
28
CRYSTAL OSC
LOW-PASS
FILTER
LOW-PASS
FILTER
D/A
CONVERTER
D/A
CONVERTER
MODE CONTROL
I/F
SERIAL INPUT
I/F
27 26 25 24 23
1
2
3
22
20 19
17
16
15
12
13
14
9
10
21
MULTI-LEVEL
DELTA-
SIGMA
MODULATOR
x8
OVERSAMPLING
DIGITAL FILTER
WITH
FUNCTION
CONTROLLER
18
ML/IIS
MC/DM1
MD/DM0
MUTE
MODE
CS/IWO
RST
VCC2L
AGND2L
ZEROR
VOUTL
VCC1
ZEROL
EXTL
11
BPZ CONTROL
CLKO
XTI
XTO
7
8
DGND
VDD
VCC2R
A
GND2R
EXTR
NC
VOUTR
AGND1
LRCK
DATA
BCK
SCK
– PANEL BOARD –
IC703
M35501P
1
2
3
4
5
6
7
8 9 10 11 12
13
14
15
16
17
18
19
20
21
22
23
24
OUTPUT CIRCUIT
SHIFT REGISTER
POWER ON
RESET
OPTIONAL DIGIT
COUNTER
DIG10
DIG9
DIG8
DIG7
DIG6
DIG5
DIG4
DIG3
DIG2
DIG1
DIG0
VEE
VSS
CLK
VCC
RESET
SEL
OVFIN
OVFOUT
DIG15
DIG14
DIG13
DIG12
DIG11
8.
IC PIN FUNCTION DESCRIPTION
• MB BOARD IC202 MB91101APFV-G-BND (DVD SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
X1/X2
O
Analog filter gain control signal output terminal Not used
2
GAIN1
O
VES gain control signal output terminal “H”: VES Not used
3
GAIN2
O
Rear channel boost control signal output terminal “H”: rear boost Not used
4
VCC
—
Power supply terminal (+3.3V)
5
CPUCK
O
CPU clock output to the gate array (IC601) (25 MHz)
6
XCS5
O
Not used (pull up)
7
XCS4
O
Chip select signal output to the gate array (IC601)
8
XCS3
O
Chip select signal output to the AV decoder (IC401)
9
XCS2
O
Chip select signal output to the AV decoder (IC401)
10
XCS1
O
Chip select signal output to the S-RAM (IC204) and gate array (IC601)
11
XCS0
O
Chip select signal output to the flash memory (IC206)
12
NMIX
I
Not used (fixed at “H”)
13
HSTX
I
Not used (fixed at “H”)
14
RSTX
I
System reset signal input from the reset signal generator (IC207) “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
15
GND
—
Ground terminal
16
MD0
I
Mode select signal input terminal Fixed at “H”
17, 18
MD1, MD2
I
Mode select signal input terminal Fixed at “L”
19
XWAIT
I
Wait signal input from the gate array (IC601)
20
TEST1
I
For test terminal Normally fixed at “H”
21
TEST2
I
For test terminal Normally fixed at “L”
22
XRD
O
Read enable signal output to the AV decoder (IC401)
23
XWRH
O
High byte write enable signal output to the flash memory (IC206), AV decoder (IC401) and
gate array (IC601)
24
XWRL
O
Low byte write enable signal output to the gate array (IC601)
25 to 39
D0 to D14
I/O
Two-way data bus terminal
40
GND
—
Ground terminal
41
D15
I/O
Two-way data bus terminal
42
A00
O
Address signal output terminal
43
VCC5
—
Power supply terminal (+3.3V)
44 to 64
A01 to A21
O
Address signal output terminal
65
GND
—
Ground terminal
66
CKSEL
O
Sampling mode selection signal output to PLL IC (IC001) “L”: standard, “H”: double
67
DIAGON
I
DIAG mode control signal input terminal “L”: DIAG Fixed at “H”
68
EOP0
I
Not used (fixed at “H”)
69
AVCC
—
Power supply terminal (+3.3V) (for A/D converter)
70
AVRH
I
Reference voltage input (+3.3V) terminal (for A/D converter)
71
AGND
—
Ground terminal (for A/D converter)
72 to 74
AN0 to AN2
I
Setting terminal for the version
75
AN3
I
Setting terminal for the version Fixed at “H”
76
SI0
I
Serial data input from the IF controller (IC1) and EEPROM (IC201)
77
SO0
O
Serial data output to the IF controller (IC1) and EEPROM (IC201)
78
SC0
O
Serial data transfer clock signal output to the IF controller (IC1) and EEPROM (IC201)
79
SI1
I
Serial data input from the audio DSP (IC501), DSD decoder (IC901) and D/A converter
(IC902, IC905 to 907)
Summary of Contents for HCD-ZX70DVD
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