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HCD-ZUX9
IC100 M30624MGP-B33FPU0 (SYSTEM CONTROL) (MAIN BOARD (1/4)) (US Model)
IC100 M30624MGP-B34FPU0 (SYSTEM CONTROL) (MAIN BOARD (1/4)) (EXCEPT US Model)
Pin No.
Pin Name
I/O
Pin Description
1
ML2252-NCR1
I
Channel 1 Next Command Ready status signal input from digital synthesizer
ML2252 “H”: Ready
2
CD_RST
O
Reset signal output to the digital signal processor
3
CD M-MUTE
O
Motor driver muting on/off control signal output
4
SIRCS
I
Remote control signal input
5
ML2252-DATA OUT
O
Serial data output to digital synthesizer ML2252
6
ML2252-NCR2
I
Channel 2 Next Command Ready status signal input from digital synthesizer
ML2252 “H”: Ready
7
ML2252-CLK
O
Serial data transfer clock signal output to digital synthesizer ML2252
8
BYTE
—
Not used. (Connected to ground)
9
CNVSS
—
Ground
10
XC-IN
I
Sub system clock input terminal (32.768kHz)
11
XC-OUT
O
Sub system clock output terminal (32.768kHz)
12
RESET
I
System reset signal input
13
X-OUT
O
Main system clock output terminal (5MHz)
14
VSS
—
Ground
15
X-IN
I
Main system clock input terminal (5MHz)
16
VCC
—
Power supply (+3.3V)
17
NMI
I
Non-maskable interrupt input (Pull up)
18
CD_BUS1/V-MUTE
I/O
Serial bus data bit 1 input/output
19
SBSY/V-OUT_SW
I
Subcode block synchronization signal input/output
20
AC_CUT
I
AC off detection signal input
21
CD_BUS2/
MIC_DETECT
I/O
Serial bus data bit 2 input/output
22
CD_BUS3/
CTR-RELAY
I/O
Serial bus data bit 3 input/output
23
CD_BUCK/
MTK-KRMOB
O
Serial data transfer clock signal output
24
CD_CCE/SW_MUTE
O
Chip enable signal output
25
CD_REQ/
ANALOG_IN_MUTE
I
Decoder request signal input
26
STBY-RELAY
O
Main power on/off control signal output “H”: power on
27
CD_A-MUTE/
DVD_A-MUTE
O
CD and USB analog signal muting signal output
28
CD_POWER/
MTK_POWER
O
Power on/off control signal output “H”: power on
29
IIC-CLK
I/O
Clock signal for IIC communication input/output
30
IIC-DATA
I/O
Data signal for IIC communication input/output
31
[MTK-SIO]
USB-POWER
O
Power on/off control signal output to USB section “H”: power on
32
[MTK-SOD]
O
Digital signal processor control bus switching signal
USB-SEL_SW
“H”: controlled by the Master Control controller “L”: controlled by USB micom
33
[MTK-CLK] USB-RST
O
Reset signal output to the USB micom
34
[MIC-STATUS]
USB-CTS0
I
Ready to receive signal input from USB micom
35
[MTK-BUSY] USB-TXD0
O
Serial data output to the USB micom
36
[MTK-XIFCS] USB-RXD0
I
Serial data input from the USB micom
37
OPEN-SW
I
Eject detection signal input from CDM
38
[MTK-RST] USB-RTS0
O
Ready to send signal to USB micom
Ver. 1.1
Summary of Contents for HCD-ZUX9
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