![background image](http://html.mh-extra.com/html/sony/hcd-vp100/hcd-vp100_service-manual_420900028.webp)
HCD-VP100
28
28
5-14.
IC PIN FUNCTION DESCRIPTION
•
MAIN BOARD IC801 CXP83124A-047Q (SYSTEM CONTROLLER, LCD DRIVER)
Pin No.
Pin Name
I/O
Description
1
TAPE-END
I
Tape end detect sensor input terminal “H” input when the tape end detected
2
(TUNED)
I
Tuning detection signal input from the tuner pack “L”: tuned
3
REMOCON
I
Sircs remote control signal input from the remote control receiver (IC802)
4
MOT-CON
O
Capstan/reel motor on/off control signal output terminal “H”: motor on
SOL-CON
O
Trigger plunger on/off control signal output terminal “H”: plunger on
6
5
T-MODE
I
Head position detect switch input terminal “L”: forward direction, “H”: reverse direction
7
REG-CON
O
Main system power supply on/off control signal output terminal “H”: power on
JOG-C (BASS)
Jog dial pulse input from the rotary encoder (RV803 BASS) (C phase input)
9
8
I
10
(TU-DATA)
O
PLL serial data output to the PLL IC on the tuner pack (at tuner function)
11
(S-CLK)
O
Serial data transfer clock signal output to the VCD block (at CD function)
Serial data output to the VCD block (at CD function)
Serial data input from the VCD block (at CD function)
12
(S-SI)
I
13
(S-SO)
O
14
(S-REQ)
O
Interrupt status output to the VCD block
15
(PBC-LED)
O
O
LED drive signal output of the PBC indicator (D860) “H”: LED on
16
JOG-D (BASS)
I
Jog dial pulse input from the rotary encoder (RV803 BASS) (D phase input)
17
(MPEG-RST)
Reset signal output to the VCD block “L”: reset
18
(TU-COUNT)
I
PLL count data input from the PLL IC on the tuner pack (at tuner function)
19
(TU-CE)
O
PLL serial chip enable signal output to the PLL IC on the tuner pack (at tuner function)
20
JOG-B
I
Jog dial pulse input from the rotary encoder (RV801 VOLUME) (B phase input)
21
JOG-A
I
O
Jog dial pulse input from the rotary encoder (RV801 VOLUME) (A phase input)
22
AMP-MUTE
O
Muting on/off control signal output to the power amplifier (IC101, 201)
“H”: muting on
23
(SCK)
Serial data transfer clock signal output to the BD3861FS (IC323)
29
Jog dial pulse input from the rotary encoder (RV802 TREBLE) (E phase input)
25
TU-ON
O
Tuner function control signal output terminal
LED drive signal output of the TUNER indicator (D856, 857) “H”: tuner power on (LED on)
26
D.S.G.
O
LED drive signal output of the DSG (Dynamic Sound Generator) indicator (D858)
“H”: LED on
27
LED drive signal output of the CD SYNC indicator (D859) “H”: LED on
28
Jog dial pulse input from the rotary encoder (RV804 FUNCTION) (G phase input)
(TU-CLK)
O
PLL serial data transfer clock signal output to the PLL IC on the tuner pack (at tuner function)
24
(MIC CHECK)
O
Microphone jack IN/OUT check detection signal output terminal
30
Jog dial pulse input from the rotary encoder (RV802 TREBLE) (F phase input)
32
Half detect (side A and B) switch and cassette in detect switch input terminal (A/D input)
33
Jog dial pulse input from the rotary encoder (RV804 FUNCTION) (H phase input)
34
KEY3
I
Key input terminal (A/D input) S816 to S820 (BAND, DSG, /–, TUNING MODE
input)
35
KEY2
I
Key input terminal (A/D input) S801 to S808 (I/
1
, CD
u
/
x
/
>
M
/
m
.
, PLAY
MODE, REPEAT, CD EJECT
Z
keys input)
36
KEY1
I
Key input terminal (A/D input
)
S809 to S815 (TAPE
n
N
/
x
/
M
/
m
/
X
, REC
z
, DC SYNC keys input)
Power supply on/off control signal output of the tuner section (FM +7.5V)
31
Pin No.
Pin Name
I/O
Description
37
SIMUKE/TEST
I
Destination setting terminal (A/D input)
38
RESET
I
System reset signal input from the reset signal generator (IC803) “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
39
EXTAL1
I
Main system clock input terminal (4.19 MHz)
40
XTAL1
O
Main system clock output terminal (4.19 MHz)
41
VSS
—
Ground terminal
42
XTAL2
O
Sub system clock output terminal (500 kHz) Not used (open)
43
EXTAL2
I
Sub system clock input terminal (500 kHz) Not used (fixed at “L”)
44
AVREF
I
Reference voltage (+5V) input terminal (for A/D conversion)
45
AVSS
—
Ground terminal (for A/D conversion)
46
VL
O
Liquid crystal display bias on/off control signal output terminal
47 to 49
VLC3 to VLC1
—
Power supply terminal for the liquid crystal display bias
50 to 53
COM0 to COM3
O
Common drive signal output to the liquid crystal display (LCD801)
54 to 85
SEG0 to SEG31
O
Segment drive signal output to the liquid crystal display (LCD801)
86
C-XRST/FM ON
O
Not used (open)
87
REC-MUTE
O
Recording muting on/off selection signal output to the Tape section
“H”: muting on, “L”: muting off
88
SDA
O
Sirial data output to the BD3861FS (IC323)
89
VDD
—
Power supply terminal (+5V)
90
NC
—
Connected to power supply (+5V)
91
VSS
—
Ground terminal
92
TX
O
Sub system clock output terminal (32.768 kHz)
93
TEX
I
Sub system clock input terminal (32.768 kHz)
94
CD-ON
O
Power supply on/off control signal output of the CD section (+5V)
LED drive signal output of the CD indicator (D852, 853) “H”: CD power on (LED on)
95
REC/PB
O
Recording/playback selection signal output to the BA3126N (IC402)
“L”: playback mode, “H”: recording mode
96
L-MUTE
O
Line muting on/off selection signal output to the Tape section
“H”: muting on, “L”: muting off
97
AU-MUTE
O
Muting on/off control signal output terminal “H”: muting on
98
TC-ON
O
Power supply on/off control signal output of the cassette holder back light
LED drive signal output of the TAPE indicator (D854, 855) “H”: back light on (LED on)
99
WP
I
Wakeup control signal input terminal
100
(S-ACK)
I
Subcode sync (S0+S1) detection signal input from the VCD block (at CD function)
w w w . x i a o y u 1 6 3 . c o m
Q Q 3 7 6 3 1 5 1 5 0
9
9
2
8
9
4
2
9
8
T E L
1 3 9 4 2 2 9 6 5 1 3
9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
TEL 13942296513 QQ 376315150 892498299
TEL 13942296513 QQ 376315150 892498299