– 26 –
Pin No.
Pin name
I/O
Description
1
VDD
–
Power supply terminal. (+5V)
2
SWDT
I
Write data signal input from the system controller (IC201).
3
SCK
I
Serial clock signal input from the system controller (IC201).
4
XLAT
I
Serial latch signal input from the system controller (IC201).
5
SRDT
O
Read data signal output to the system controller (IC201).
6
SENSE
O
Internal status (SENSE) output to the system controller (IC201).
7
SCMD0
I
Serial command control mode input from the system controller. (Fixed at “H”)
8
SCMD1
I
Serial command control mode input from the system controller. (Fixed at “H”)
9
XINT
O
Interruption status output to the system controller (IC201).
10
RCPB
I
Record/playback selection signal input. Not used this set. (Fixed at “L”)
11
WRMN
I
Write/monitor mode selection signal input from the system controller (IC201).
12
TX
–
Writing data transmission timing input from the system controller (IC201).
Used together with the magnetic field head ON/OFF output.
13
VSS
–
Ground terminal.
14
SICK
I
Chip reserve terminal. (Fixed at “L”)
15
IDSL
I
Chip reserve terminal. (Fixed at “L”)
16
XILT
I
Chip reserve terminal. (Fixed at “H”)
17
XRST
I
Reset signal input from the system controller (IC201).
When reset : “L”
18–21
TS0–TS3
I
Test input terminal. (Fixed at “L”)
22
EXIR
I
Chip reserve terminal. (Fixed at “L”)
23
SASL
I
Single use the block selection. “L” : ATRAC, “H” : RAM Controller (Fixed at “L”)
24
SNGLE
I
Normally fixed at “L”, Fixed at “H” when the ATRAC or RAM controller is single used.
(Fixed at “L”)
25
VSS
–
Ground terminal.
26
AIRCPB
O
Record/playback mode signal output terminal of the ATRAC or external audio block.
Not
used this set.
27
XRQ
I/O
XRQ signal input/output terminal of the ATRAC interface. Not used this set.
28
ADTO
I/O
Decoder data signal input/output terminal of the ATRAC. Not used this set.
29
ADTI
I/O
Encoder data signal input/output terminal of the ATRAC. Not used this set.
30
XALT
I/O
XALT signal input/output terminal of the ATRAC interface. Not used this set.
31
ACK
I/O
ACK signal input/output terminal of the ATRAC interface. Not used this set.
32
AC2
I/O
Error data signal input/output terminal of the ATRAC interface. Not used this set.
33
LCHST
I/O
Lch Start data signal input/output terminal of the ATRAC interface. Not used this set.
34
EXE
I/O
EXE signal input/output terminal of the ATRAC interface. Not used this set.
35
MUTE
I/O
MUTE signal input/output terminal of the ATRAC interface. Not used this set.
36
OSCO
O
45MHz clock oscillation output. (45MHz)
37
OSCI
I
45MHz clock oscillation input. (45MHz)
38
VSS
–
Ground terminal.
39
ATT
I/O
ATT signal input/output terminal of the ATRAC interface. Not used this set.
40
F86
O
11.6msec timing signal output terminal of the ATRAC block. Not used this set.
41
DOUT
O
Monitor/audio decode data signal output to the D/A converter (IC281).
42
ADIN
I
Recoding data signal input from the D/A converter (IC261).
43
ABCK
O
Bit clock signal output to the A/D, D/A converter (IC261, 281).
44
ALRCK
O
L/R clock signal output to the A/D, D/A converter (IC261, 281).
45-47
SA2-SA0
O
Address signal output. Not used this set (OPEN)
48,49
A11,A10
O
Address signal output. Not used this set
IC271 SHCCK PROOF MEMORY CONTROLLER, ATRAC ENCODER/DECODER (CXD2536R)
Summary of Contents for HCD-MJ1
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